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Unformatted text preview: forms a ring ¾Û ½ ¾ ½ +tÛ *tÛ -tÛ ¼ ½ . 2.3.6 Multiplying by Powers of Two
On most machines, the integer multiply instruction is fairly slow—requiring 12 or more clock cycles— whereas other integer operations such as addition, subtraction, bit-level operations, and shifting require only one clock cycle. As a consequence, one important optimization used by compilers is to attempt to replace multiplications by constant factors with combinations of shift and addition operations. Let Ü be the unsigned integer represented by bit pattern ÜÛ ½ ÜÛ ¾ claim the bit-level representation of Ü¾ is given by ÜÛ ½ ÜÛ ¾ Ü¼ Ü¼ .
¼ Then for any ¼, we ¼ , where 0s have been 64 CHAPTER 2. REPRESENTING AND MANIPULATING INFORMATION added to the right. This property can be derived using Equation 2.1: ¾Í Û· ´ Ü ½ Ü ¾
Û Û Ü¼ Û ½
¼ ¼ ¼µ Ü¾· Ü¾ Û ½
¼ ¡ ¾ Ü¾ For Û, we can truncate the shifted bit vector to be of length Û, giving ÜÛ ½ ÜÛ ¾ Ü¼ ¼ ¼. By Equation 2.7, this bit-vector has numeric value Ü¾ ÑÓ ¾Û Ü *u ¾ . Thus...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.
- Spring '10
- The American