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Unformatted text preview: We will discuss the special case, where , in the next section. Figure 6.32 shows the organization of a two-way set associative cache. 314 valid valid valid valid tag tag tag tag ••• set S-1: valid valid tag tag CHAPTER 6. THE MEMORY HIERARCHY cache block cache block cache block cache block set 0: E=2 lines per set set 1: cache block cache block Figure 6.32: Set associative cache (½ ). In a set associative cache, each set contains more than one line. This particular example shows a 2-way set associative cache. Set Selection in Set Associative Caches Set selection is identical to a direct-mapped cache, with the set index bits identifying the set. Figure 6.33 summarizes this. set 0: valid valid valid valid tag tag tag tag ••• valid t bits m-1 cache block cache block cache block cache block Selected set set 1: tag tag cache block cache block tag s bits b bits 00 001 set index block offset set S-1: 0 valid Figure 6.33: Set selection in a set associative cache. Line Matching and Word Selection in Set Associative Caches Line matching is more involved in a set associative cache than in a direct-mapped cache because it must check the tags and valid bits...
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