Thus the time to read a 512 byte sector sized block

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: mory controller. In this case, when the controller receives an address , the controller selects the module that contains , converts to its ´ µ form, and sends ´ µ to module . Practice Problem 6.1: In the following, let Ö be the number of rows in a DRAM array, the number of columns, Ö the number of bits needed to address the rows, and the number of bits needed to address the columns. For each of the following DRAMs, determine the power-of-two array dimensions that minimize Ñ Ü´ Ö µ, the maximum number of bits needed to address the rows or columns of the array. Organization Ö ¢½ ¢ ½¾ ¢ ½¾ ¢ ½¼¾ ¢ ½ ½ Ö Ñ Ü´ Ö µ Enhanced DRAMs There are many kinds of DRAM memories, and new kinds appear on the market with regularity as manufacturers attempt to keep up with rapidly increasing processor speeds. Each is based on the conventional DRAM cell, with optimizations that improve the speed with which the basic DRAM cells can be accessed. ¯ Fast page mode DRAM (FPM DRAM). A conventional DRAM copies an entire row of supercells into its internal row buffer, uses one, and then discards the rest. FPM DRAM improves on this by allowing consecutive accesses to t...
View Full Document

This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Ask a homework question - tutors are online