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Unformatted text preview: erational view of a TLB hit and miss. 10.6. ADDRESS TRANSLATION 503 in memory at all times, even if the application referenced only a small chunk of the virtual address space. The problem is compounded for systems with 64-bit addresses spaces. The common approach for compacting the page table is to a use a hierarchy of page tables instead. The idea is easiest to understand with a concrete example. Suppose the 32-bit virtual address space is partitioned into four-KB pages, and that page table entries are four bytes each. Suppose also that at this point in time the virtual address space has the following form: The first 2K pages of memory are allocated for code and data, the next 6K pages are unallocated, the next 1023 pages are also unallocated, and the next page is allocated for the user stack. Figure 10.18 shows how we might construct a two-level page table hierarchy for this virtual address space. Level 1 Page Table Level 2 Page Tables Virtual Memory 0 VP 0 PTE 0 PTE 1 PTE 2 (null) PTE 3 (null) PTE 4 (n...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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