Using the memory mountain in figure 642 estimate the

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ches result in fewer transfers, which allows more bandwidth to memory for I/O devices that perform DMA. Further, reducing the number of transfers becomes increasingly important as we move down the hierarchy and the transfer times increase. In general, caches further down the hierarchy are more likely to use write-back than write-through. Aside: Cache lines, sets, and blocks: What’s the difference? It is easy to confuse the distinction between cache lines, sets, and blocks. Let’s review these ideas and make sure they are clear: ¯ ¯ ¯ A block is a fixed sized packet of information that moves back and forth between a cache and main memory (or a lower level cache). A line is a container in a cache that stores a block, as well as other information such as the valid bit and the tag bits. A set is a collection of one or more lines. Sets in direct-mapped caches consist of a single line. Sets in set associative and fully associative caches consist of multiple lines. 322 CHAPTER 6. THE MEMORY HIERARCHY In dir...
View Full Document

This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Ask a homework question - tutors are online