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Unformatted text preview: et contains all 316 CHAPTER 6. THE MEMORY HIERARCHY Set Selection in Fully Associative Caches Set selection in a fully associative cache is trivial because there is only one set. Figure 6.36 summarizes. Notice that there are no set index bits in the address, which is partitioned into only a tag and a block offset. valid The entire cache is one set, so by default set 0 is always selected. t bits m-1 tag tag ••• tag cache block cache block cache block Set 0: valid valid b bits block offset 0 tag Figure 6.36: Set selection in a fully associative cache. Notice that there are no set index bits Line Matching and Word Selection in Fully Associative Caches Line matching and word selection in a fully associative cache work the same as with an associated cache, as we show in Figure 6.37. The difference is mainly a question of scale. Because the cache circuitry =1 ? (1) The valid bit must be set. 0 1 2 3 4 5 6 7 1 0 entire cache 1 0 1001 0110 0110 1110 w0 w1 w2 w3 (2) The tag bits in one of the cache lines must match the tag bits in the address =? t bits 0110...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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