Aij i0 i1 i2 i3 j0 1 m 2 m 3 m 4 m j1 5 m

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Unformatted text preview: ) The valid bit must be set. 0 1 2 3 4 5 6 7 315 1 selected set (i): 1 1001 0110 w0 w1 w2 w3 (2) The tag bits in one of the cache lines must match the tag bits in the address =? (3) If (1) and (2), then cache hit, and block offset selects starting byte. s bits b bits i 100 set index block offset m-1 t bits 0110 tag 0 Figure 6.34: Line matching and word selection in a set associative cache. Line Replacement on Misses in Set Associative Caches If the word requested by the CPU is not stored in any of the lines in the set, then we have a cache miss, and the cache must fetch the block that contains the word from memory. However, once the cache as retrieved the block, which line should it replace? Of course, if there is an empty line, then it would be a good candidate. But if there are no empty lines in the set, then we must choose one of them and hope that the CPU doesn’t reference the replaced line anytime soon. It is very difficult for programmers to exploit knowledge of the cache replacement policy in their codes, so we will not go into much detail. The simplest replacement policy is to choose the line to replace at random. Other more sophisticated policies draw on the principl...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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