H define timeout 5 void threadvoid vargp struct

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: -4(%ebp),%eax cmpl $99999999,%eax jle .L12 jmp .L10 .L12: movl ctr,%eax leal 1(%eax),%edx movl %edx,ctr .L11: movl -4(%ebp),%eax leal 1(%eax),%edx movl %edx,-4(%ebp) jmp .L9 .L10: 575 Hi : Head C code for thread i for (i=0; i<NITERS; i++) ctr++; Li : Load ctr Ui : Update ctr Si : Store ctr Ti : Tail Figure 11.9: IA32 assembly code for the counter loop in badcnt.c. can be interleaved in any order, so long as the instructions for each thread execute in program order. For example, the ordering À½ À¾ Ľ ľ ͽ ; ˽ ˾ ̽ ̾ À½ À¾ ͽ ľ Ľ ; ˽ ˾ ̽ ̾ is sequentially consistent, while the ordering is not sequentially consistent because ͽ executes before Ľ . Unfortunately not all sequentially consistent orderings are created equal. Some will produce correct results, but others will not, and there is no way for us to predict whether the operating system will choose a correct ordering for our threads. For example, Figure 11.10(a) shows the step-by-step operation of a co...
View Full Document

This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Ask a homework question - tutors are online