Set by mmu on reads and writes cleared by software

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Unformatted text preview: s the general idea. Page tables with permission bits SUP READ WRITE Process i: VP 0: VP 1: VP 2: no no yes yes yes yes no yes yes • • • Address PP 9 PP 4 PP 2 Physical memory PP 0 PP 2 PP 4 PP 6 SUP READ WRITE Process j: VP 0: VP 1: VP 2: no yes no yes yes yes no yes yes • • • Address PP 9 PP 6 PP 11 PP 9 PP 11 • • • Figure 10.11: Using VM to provide page-level memory protection. In this example, we have added three permission bits to each PTE. The SUP bit indicates whether processes must be running in kernel (supervisor) mode to access the page. Processes running in kernel mode can 10.6. ADDRESS TRANSLATION Basic parameters Description Number of addresses in virtual address space Number of addresses in physical address space Page size (bytes) Components of a virtual address (VA) Description Virtual page offset (bytes) Virtual page number TLB index TLB tag Components of a physical address (PA) Description Physical page offset (bytes) Physical page number Byte offset wit...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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