324_Book

# Strtab a string table for the symbol tables in the

This preview shows page 1. Sign up to view the full content.

This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ( ). Cache 1. 2. 3. 4. 5. 6. Ñ Ë Ø × 32 32 32 32 32 32 1024 1024 1024 1024 1024 1024 4 4 8 8 32 32 4 256 1 128 1 4 Homework Problem 6.22 [Category 1]: This problem concerns the cache in Problem 6.9. A. List all of the hex memory addresses that will hit in Set 1. B. List all of the hex memory addresses that will hit in Set 6. Homework Problem 6.23 [Category 2]: Consider the following matrix transpose routine: 1 2 typedef int array[4][4]; 340 3 4 5 6 7 8 9 10 11 12 CHAPTER 6. THE MEMORY HIERARCHY void transpose2(array dst, array src) { int i, j; for (i = 0; i &lt; 4; i++) { for (j = 0; j &lt; 4; j++) { dst[j][i] = src[i][j]; } } } Assume this code runs on a machine with the following properties: ¯ ¯ ¯ ¯ ¯ sizeof(int) == 4. The src array starts at address 0 and the dst array starts at address 64 (decimal). There is a single L1 data cache that is direct-mapped, write-through, write-allocate,with a block size of 16 bytes. The cache has a total size of 32 data bytes and the cache is initially empty. Accesses to the src and dst arrays are...
View Full Document

## This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Ask a homework question - tutors are online