Virtual address 20 12 cpu vpn 16 vpo 4 tlbt tlbi tlb

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Unformatted text preview: ns the requested data word to the processor. Unlike a page hit, which is handled entirely by hardware, handling a page fault requires cooperation between hardware and the operating system kernel (Figure 10.14(b)). ¯ Steps 1 to 3: The same as Steps 1 to 3 in Figure 10.14(a). 10.6. ADDRESS TRANSLATION 499 CPU chip 2 PTEA 1 PTE MMU 3 Processor VA PA 4 cache/ memory data 5 (a) Page hit. 4 exception page fault exception handler CPU chip 2 PTEA 1 victim page cache/ memory 5 Processor VA 7 MMU PTE 3 disk new page 6 (b) Page fault. Figure 10.14: Operational view of page hits and page faults. VA: virtual address. PTEA: page table entry address. PTE: page table entry. PA: physical address. 500 CHAPTER 10. VIRTUAL MEMORY ¯ ¯ ¯ ¯ Step 4: The valid bit in the PTE is zero, so the MMU triggers an exception, which transfers control in the CPU to a page fault exception handler in the operating system kernel. Step 5: The fault handler identifies a victim page in physical memory, and if that page has been modified,...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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