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Unformatted text preview: e performed inside the on-chip MMU, and thus are fast. ¯ ¯ ¯ ¯ Step 1: The CPU generates a virtual address. Steps 2 and 3: The MMU fetches the appropriate PTE from the TLB. Step 4: The MMU translates the virtual address to a physical address and sends it to the cache/main memory. Step 5: The cache/main memory returns the requested data word to the CPU. When there is a TLB miss, then the MMU must fetch the PTE from the L1 cache, as shown in Figure 10.17(b). The newly fetched PTE is stored in the TLB, possibly overwriting an existing entry. 10.6.3 Multi-level Page Tables
To this point we have assumed that the system uses a single page table to do address translation. But if we had a 32-bit address space, 4-KB pages, and a 4-byte PTE, then we would need a 4-MB page table resident 502 CHAPTER 10. VIRTUAL MEMORY CPU chip TLB
2 VPN PTE 3 1 Processor VA Translation 4 PA cache/ memory 5 data (a) TLB hit.
CPU chip TLB
4 2 VPN PTE 3 PTEA
1 Processor VA Translation PA
5 cache/ memory data
6 (b) TLB miss. Figure 10.17: Op...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.
- Spring '10
- The American