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Unformatted text preview: m-1 tag b bits 100 block offset (3) If (1) and (2), then cache hit, and block offset selects starting byte. 0 Figure 6.37: Line matching and word selection in a fully associative cache. must search for many matching tags in parallel, it is difficult and expensive to build an associative cache that is both large and fast. As a result, fully associative caches are only appropriate for small caches, such as the translation lookaside buffers (TLBs) in virtual memory systems that cache page table entries (Section 10.6.2). Practice Problem 6.9: The following problems will help reinforce your understanding of how caches work. Assume the following: ¯ ¯ The memory is byte addressable. Memory accesses are to 1-byte words (not 4-byte words). 6.4. CACHE MEMORIES 317 ¯ ¯ Addresses are 13 bits wide. The cache is 2-way set associative ( ¾), with a 4-byte block size ( ) and 8 sets (Ë ). The contents of the cache are as follows. All numbers are given in hexadecimal notation. 2-way Set Associativ...
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This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

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