mid2w10sol - ECEn 324 Winter 2010 Midterm #2 Solution 1. a....

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECEn 324 Winter 2010 Midterm #2 Solution 1. Which of the following is NOT true of the Y86 ISA? a. Target addresses for jump instructions are represented as absolute addresses in 4 bytes. b. Instructions with explicit register operands can be as short as a single byte. c. It has no scaled addressing modes. d. Even small immediate values require 4 bytes to represent. Solution: Option a is certainly true: this is the key to being able to predict branches as taken by the end of the cycle on which the instruction is fetched. (Otherwise there would be some calculation required that would take additional cycles.) Choice c is also true: note for example the discussion on page 266 about the difficulty of converting array indexing IA32 code to Y86 instructions. Choice d is also true as Figure 4.2 clearly shows. That leaves us with choice b. It is important to note that an entire byte is always used to encode the register specifiers for instructions that require registers. Therefore, any instruction that explicitly references operands will require at least two bytes. 2. Which of the statements below is true about the combinational logic circuit represented by this HCL code? int Unknown1 = [ A >= B && A >= C : A; B >= A && B >= C : B; 1 : C; ] ; a. The circuit is a functional 3-to-1 word-level MUX. b. The circuit correctly finds the minimum value among a set of 3 words. c. The circuit correctly finds the median value among a set of 3 words. d. The circuit correctly finds the maximum value among a set of 3 words. e. None of the above Solution: This code is a correct specification of a circuit that picks the largest of the three input words. 3. Which of the Y86 instructions below matches this sequence of operations in its sequential implementation? Fetch icode:ifun M 1 [PC] rA:rB M 1 [PC+1] valC M 4 [PC+2] valP PC + 6 Decode valA R[rA] valB R[rB] Execute valE valB + valC Memory M 4 [valE] valA Writeback PC update PC valP a. rmmovl b. mrmovl c. irmovl
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 d. pushl e. call Solution: With a bit of reflection, the answer should be relatively easy to determine. First, notice that the instruction is writing a register value to memory. That limits the possibilities to rmmovl, pushl, and call, and the latter two can be eliminated by noting that this instruction does not reference the stack pointer. The correct answer is therefore a. 4. Which of the following is the LEAST likely consequence of increasing the pipelining depth? a. increased overhead due to the delay of pipeline registers b. increased latency of execution of each operation c. increased frequency of mispredicted branches d. increased number of stalls resulting from data dependencies Solution: As Figure 4.37 (and associated discussion in the text) shows, a is a very likely consequence. The longer pipe will inevitably increase the time required for operations (or instructions) to go from one end of the pipe to the other, so b is also true. Choice c is not true: the misprediction penalty
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/02/2010 for the course ELECTRICAL 360 taught by Professor Schultz during the Spring '10 term at BYU.

Page1 / 9

mid2w10sol - ECEn 324 Winter 2010 Midterm #2 Solution 1. a....

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online