CS211Lecture5Module6

CS211Lecture5Module6 - CS 211: Computer Architecture...

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CS 211: Computer Architecture Lecture 5 Instruction Level Parallelism and Its Dynamic Exploitation Instructor: M. Lancaster
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06/5/2008 Lecture 5 Summer 2008 2 Hardware Based Speculation For highly parallel machines, maintaining control dependencies is difficult A processor executing multiple instructions per clock may need to execute a branch instruction every clock. The processor will speculate (guess) on the outcome of branches and execute the program as if the guesses are correct. Fetch, issue and execute instructions as if they are correct; dynamic scheduling only fetches and issues the instructions Must handle incorrect speculations
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06/5/2008 Lecture 5 Summer 2008 3 Hardware Based Speculation Combination of 3 key activities Dynamic branch prediction to choose which instructions to execute Speculation to allow the execution of instructions before the control dependencies are resolved Must be able to undo effects of an incorrectly speculated sequence Dynamic scheduling to deal with scheduling of different combinations of basic blocks Hardware based speculation follows the predicted flow of data values to choose when to execute instructions
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06/5/2008 Lecture 5 Summer 2008 4 Hardware Based Speculation Approach A particular approach is an extension of Tomasulo’s algorithm. Extend the hardware to support speculation Separate the bypassing of results among instructions from the actual completion of an instruction, allowing an instruction to execute and to bypass its results to other instructions without allowing the instruction to perform any updates that cannot be undone When an instruction is no longer speculative, it is committed. (An extra step in the instruction execution sequence allows it to update the register file or memory – “instruction commit”.
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06/5/2008 Lecture 5 Summer 2008 5 Hardware Based Speculation Approach Allow instructions to execute out of order but force them to commit in order to prevent irrevocable actions such as updating state or taking an exception Add a commit phase (to our 5 stage pipeline as an example) Requires changes to the sequence and additional set of hardware buffers that hold the results of instructions that have finished but not committed. The hardware buffer is called a ReOrder Buffer (ROB)
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Lecture 5 Summer 2008 6 Reorder Buffer (ROB) Provides additional registers in the same way as the reservation stations Holds result of instruction between the time the operation associated with the instruction completes and the time the instruction commits. It therefore is a source of operands for instructions
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CS211Lecture5Module6 - CS 211: Computer Architecture...

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