mtS10 Solutions

mtS10 Solutions - SOLUTIONS San Jose State University CmpE...

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Unformatted text preview: SOLUTIONS San Jose State University CmpE 102 Name __________________ Midterm Exam ID # ___________________ Spring 2010 This midterm examination is OPEN book and notes, but shall be your own work. Do not assume anything, but ask the instructor for clarification on exam questions. *********************************************************************** * A. Small Problems (35 pts) (5 pts each unless otherwise specified) 1. What was the original intent of the RISC architecture? To develop a small instruction set with simple instructions running out of hardware in the silicon. The intent of RISC was to execute many simple instructions at a fast speed (ideally, 1 clock/instruction), and supposedly faster than a complex instruction of a CISC architecture. Also, to provide many on-chip registers for temporary data storage, thus, eliminating the longer off-chip memory access times. 2. Convert the decimal number 3.141593 ( ) to binary, showing all your calculations and include sufficient resolution. Integer portion: 3 10 => 11 2 Fractional portion: 0.141593 x 2 = .283186 (2-1 = .5) 0.283186 x 2 = .566372 (2-2 = .25) 0.566372 x 2 = 1 .132744 (2-3 = .125 ) 0.132744 x 2 = .265488 (2-4 = .0625) 0.265488 x 2 = .530976 (2-5 = .03125) 0.530976 x 2 = 1 .061952 (2-6 = .015625 ) 0.061952 x 2 = .123904 (2-7 = .0078125) 0.123904 x 2 = .247808 (2-8 = .00390625) 0.247808 x 2 = .495616 (2-9 = .001953125) 0.495616 x 2 = .991232 (2-10 = .0009765625) 0.991232 x 2 = 1 .982464 (2-11 = .00048828125 ) 0.982464 x 2 = 1 .964928 (2-12 = .000244140625 ) 0.964928 x 2 = 1 .929856 (2-13 = .0001220703125 ) 0.929856 x 2 = 1 .859712 (2-14 = .00006103515625 ) 0.859712 x 2 = 1 .719424 (2-15 = .000030517578125 ) 0.719424 x 2 = 1 .438848 (2-16 = .0000152587890625 ) Final Result = 11.0010010000111111, which is equivalent to 3.1415863. If this resolution is not adequate, then additional binary bits must be added to the fractional result. 3. Explain segment override and its performance cost to a bus cycle. The different registers in the instruction set have default segment registers assigned to each. If a different segment register is and can be used with the register, then the use of a new segment register represents a segment override. Example: mov ax, [esi], where ds is the default segment register. mov ax, cs:[esi] changes the segment register to cs , which is now a segment override to the esi register. The performance penalty for a segment override is two clocks per instruction execution. 4. Show the position of the stack pointer and memory addresses and contents of the stack at completion of the 7 instructions. (10 pts) .code mov ax,8000h mov ss,ax mov esp,1000h push ax push bx push cx call InputSample ; 5 byte instruction located at EC0Fh SS = 8000h, ESP = 00001000h Stack Area: 80000h 80FFFh Memory Stack Stack Address Contents Pointer 81000h ? 00001000h 80FFEh (ax) 00000FFEh 80FFCh (bx) 00000FFCh 80FFAh (cx) 00000FFAh 80FF8h EC14h 00000FF8h 5.5....
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mtS10 Solutions - SOLUTIONS San Jose State University CmpE...

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