ch8 - Silberschatz, Galvin and Gagne ©2007 Operating...

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Unformatted text preview: Silberschatz, Galvin and Gagne ©2007 Operating System Concepts with Java – 7 th Edition, Nov 15, 2006 Chapter 8: Main Memory 8.2 Silberschatz, Galvin and Gagne ©2007 Operating System Concepts with Java – 7 th Edition, Nov 15, 2006 Chapter 8: Memory Management ¡ Background ¡ Swapping ¡ Contiguous Memory Allocation ¡ Paging ¡ Structure of the Page Table ¡ Segmentation ¡ Example: The Intel Pentium 8.3 Silberschatz, Galvin and Gagne ©2007 Operating System Concepts with Java – 7 th Edition, Nov 15, 2006 Objectives ¡ To provide a detailed description of various ways of organizing memory hardware ¡ To discuss various memory-management techniques, including paging and segmentation ¡ To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging 8.4 Silberschatz, Galvin and Gagne ©2007 Operating System Concepts with Java – 7 th Edition, Nov 15, 2006 Background ¡ Program must be brought (from disk) into memory and placed within a process for it to be run ¡ Main memory and registers are only storage CPU can access directly ¡ Register access in one CPU clock (or less) ¡ Main memory can take many cycles ¡ Cache sits between main memory and CPU registers ¡ Protection of memory required to ensure correct operation 8.5 Silberschatz, Galvin and Gagne ©2007 Operating System Concepts with Java – 7 th Edition, Nov 15, 2006 Base and Limit Registers ¡ A pair of base and limit registers define the logical address space 8.6 Silberschatz, Galvin and Gagne ©2007 Operating System Concepts with Java – 7 th Edition, Nov 15, 2006 Binding of Instructions and Data to Memory ¡ Address binding of instructions and data to memory addresses can happen at three different stages ¢ Compile time : If memory location known a priori, absolute code can be generated; must recompile code if starting location changes ¢ Load time : Must generate relocatable code if memory location is not known at compile time ¢ Execution time : Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers) 8.7 Silberschatz, Galvin and Gagne ©2007 Operating System Concepts with Java – 7 th Edition, Nov 15, 2006 Multistep Processing of a User Program 8.8 Silberschatz, Galvin and Gagne ©2007 Operating System Concepts with Java – 7 th Edition, Nov 15, 2006 Logical vs. Physical Address Space ¡ The concept of a logical address space that is bound to a separate physical address space is central to proper memory management ¢ Logical address – generated by the CPU; also referred to as virtual address ¢ Physical address – address seen by the memory unit ¡ Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address- binding scheme 8.9 Silberschatz, Galvin and Gagne ©2007 Operating System Concepts with Java – 7...
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ch8 - Silberschatz, Galvin and Gagne ©2007 Operating...

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