hw - HW2(Due November 13th 1 Assume the contents of $1 and...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: HW2 (Due November 13th) 1. Assume the contents of $1 and $2 are ox10, and ox20. Fill the values at Qs for instruction beq $1,$2,100. Q26 Instruction [25– 0] 26 Shift left 2 Q25a Q21 Q25b 28 0 4 Instruction [31– 26] PC Instruction memory Instruction [15– 11] Q22 Q18a 0 M u x 1 Instruction [15– 0] Read data 1 Read register 2 Registers Read Write data 2 register 0 M u x 1 Write data 16 Sign extend 000100 00001 00010 Zero ALU ALU result Q18b 32 ALU control Instruction [5– 0] Branch Q20 Q17 Read register 1 Instruction [20– 16] Instruction [31– 0] 0 Shift left 2 RegDst Jump Branch MemRead Control MemtoReg ALUOp MemWrite ALUSrc RegWrite Instruction [25– 21] Read address M u x 1 Q24 1 M u x LU Add reAult s Q16 Q27 Jump address [31– 0] PC+4 [31– 28] Add Q23 0000000000011001 Address Write data Read data Data memory Q19 beq $1,$2,100 1 M u x 0 2. Fill the values at Qs for instruction add $1,$2,$3. Assume the contents of $1, $2, $3 are ox10, ox20, and ox30. Instruction [25– 0] 26 Shift left 2 Jump address [31– 0] 28 0 LU Add reAult s Add 4 Q7 Instruction [31– 26] Q8 PC Instruction [31– 0] Instruction memory Q10a Q9 Instruction [15– 11] Instruction [15– 0] Q15 Add 0 M u x 1 Q14a Q11b Q12 Read register 1 Instruction [20– 16] 0 Shift left 2 RegDst Jump Branch MemRead Control MemtoReg ALUOp MemWrite ALUSrc RegWrite Instruction [25– 21] Read address M u x 1 PC+4 [31– 28] 1 M u x Q13 Read data 1 Read register 2 Registers Read Write data 2 register 0 M u x 1 Write data Zero ALU ALU result Address Write data Q10b6 1 Sign extend Data memory 32 ALU control Instruction [5– 0] Q11a Read data 000000 00010 00011 00001 00000 010000 Q14b add $1,$2,$3 1 M u x 0 3. Shown here is the hardware description of the final algorithm of the multiplication. Assume that both multiplicand and the multiplier are both 4 bits and therefore, the product register is 8 bits, show step by step the multiplication of 0010 by 1011. You can use the following example format. 4. Given the architecture diagram as shown below, fill in the values at ? locations in the following finite state machine. There are total of 10? in the FSM. The control signals are connected to the outputs control unit. 2 M m ry eo access ') SW ''SW 3 A USrcA=1 L A USrcB= ? L A UO = 10 Lp 5 M m ead eR IorD = 1 4 Banch r c m letio op n 8 A U rcA= 1 LS A USrcB= ? L A UOp= ? L PCWiteC n r od PCSo rce = ? u p= (O (O = 'LW) p ' A USrcA= ? L A USrcB= 10 L A UO = ? Lp (Op e p) R-ty = Wite-b ckstep ra RegD t=0 s RegWite r M moReg=1 et M m ry eo access M m rite eW IorD= ? 7 R-type com letion p Reg st = 1 D RegWite r M mo eg= 0 e tR 9 (Op='J) ' ') 'SW (Op= Execuio tn 'r W) o p= 'L 6 (O M m ryadd ess eo r co puation mt A USrcA= 0 L A USrcB= ? L A UOp= 00 L 'BE Q') Start Insru tiond co e/ tc ed regster fetch i 1 (O p= Instru tio fetch cn 0 M m ead eR A USrcA= 0 L IorD= 0 IRWite r A USrcB= ? L A UO = 00 Lp PCWite r PCSo rce = 00 u Jum p com letion p PCWite r PCSo rce = ? u 5. Given the control signals identified in the following diagram, fill the blacks in the table. PCSrc 0 M u x 1 IF/ID ID/EX EX/MEM MEM/WB Add Shift left 2 Address Instructi on memory Instruction RegWri te PC Ad d result Add 4 Read register 1 Branch MemWrite Read data 1 Read register 2 R egi sters Read Write data 2 register Write data ALU Src Zo Zerero ALU ALU result 0 M u x 1 MemtoReg Address Data memory Write Read data 1 M u x 0 data Instruction 16 [15– 0] Si gn extend 32 Instruction [20– 16] Instruction [15– 11] 6 0 M u x 1 AL U control MemRead ALUOp RegDst Instruction Add $1,$2,$3 LW $2,3($4) Execution/address calculation stage control signal Reg/Dst ALUOp1 ALUOp2 ALUSrc Memory access stage control lines Branch MemRead MemWrite WB stage control lines RegWrite Memto Reg 6. Modify the following sequence of instructions using a delayed branch to eliminate as many stalls as possible. We don’t know if the branch is taken or not. State your assumptions if any. add $7, $3, $2 sub $5, $6, $2 add $4, $7, $2 beq $7, $4, label1 7. Given that the base CPI of a system is 1.0, miss rate data = 9%, miss rate instructions = 5%. Loads and stores make up 45% of instructions. Calculate the total CPI for instructions and data and also the % of time used for accessing memory in this system. 8. For the following sequence of byte addresses 0, 16, 45, 8, 32, 7, 10, 56, 39, 72, given 8 byte blocks and a 12-block cache, determine misses and hits for; i. ii. iii. iv. A direct mapped cache A 2 way set associative cache A 4 way set associative cache A fully associative cache. 9. Given that the base CPI of a cache system is 2.0. For a clock speed of 1GHz, memory access time is 50cc, a hit rate of 93% in level 1 cache, calculate: v. The memory access time for this system. vi. If we include a 2nd level cache with access time = 5cc and a hit rate of 96%, calculate the memory access time with this new cache included. ...
View Full Document

{[ snackBarMessage ]}

Ask a homework question - tutors are online