ece5440_RTL

# ece5440_RTL - Verilog for Digital Design Chapter 5 RTL...

This preview shows pages 1–7. Sign up to view the full content.

1 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky Verilog for Digital Design Chapter 5: RTL Design

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
2 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky High-Level State Machine Behavior
3 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky High-Level State Machine Behavior Register-transfer level (RTL) design captures desired system behavior using high-level state machine – Earlier example – 3 cycles high, used FSM – What if 512 cycles high? 512-state FSM? – Better solution – High-level state machine that uses register to count cycles • Declare explicit register Cnt (2 bits for 3- cycles high) • Initialize Cnt to 2 (2, 1, 0 Æ 3 counts) •"O n " s t a t e –S e t s X = 1 – Configures Cnt for decrement on next cycle – Transitions to Off when Cnt is 0 – Note that transition conditions use current value of Cnt, not next (decremented) value • For 512 cycles high, just initialize Cnt to 511 Inputs: B; Outputs: X On2 On1 On3 Off X=1 X=1 X=1 X=0 B' B 3 cycles with X=1 Inputs: B; Outputs: X; On Off X=1 X=0 B' B 3 cycles with X=1 Register: Cnt(2) Cnt=2 Cnt=Cnt-1 (Cnt=0)' Cnt=0

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
4 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky Combinational logic State register State x b clk FSM inputs outputs StateNext High-Level State Machine Behavior Module ports same as FSM Same two-procedure approach as FSM – One for combinational logic, one for registers – Registers now include explicit registers ( Cnt ) • Two reg variables per explicit register ( current and next ), just like for state register `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On = 1; reg [0:0] State, StateNext; reg [1:0] Cnt, CntNext; // CombLogic always @(State, Cnt, B) begin ... end // Regs always @(posedge Clk) begin ... end endmodule vldd_ch5_LaserTimerHLSM.v Combinational logic State register State X B Clk HLSM StateNext Cnt register Cnt CntNext
5 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky High-Level State Machine Behavior CombLogic process – Describes actions and transitions ... reg [0:0] State, StateNext; reg [1:0] Cnt , CntNext ; // CombLogic always @(State, Cnt, B) begin case (State) S_Off: begin X <= 0; CntNext <= 2; if (B == 0) StateNext <= S_Off; else StateNext <= S_On; end S_On: begin X <= 1; CntNext <= Cnt -1 ; if ( Cnt == 0) StateNext <= S_Off; else StateNext <= S_On; end endcase end ... vldd_ch5_LaserTimerHLSM.v Combinational logic State register State X B Clk HLSM inputs outputs StateNext Cnt register Cnt CntNext Note: Writes are to " next " variable, reads are from " current " variable. See target architecture to understand why. Inputs: B; Outputs: X; On Off X=1 X=0 B' B Register: Cnt(2) Cnt=2 Cnt=Cnt-1 (Cnt=0)' Cnt=0

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
6 Verilog for Digital Design Copyright © 2007 Frank Vahid and Roman Lysecky High-Level State Machine Behavior Regs process – Updates registers on rising clock ...
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 45

ece5440_RTL - Verilog for Digital Design Chapter 5 RTL...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online