exam2 - ECE 5367 Introduction to Computer Architecture Exam...

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Unformatted text preview: ECE 5367 Introduction to Computer Architecture Exam 2 Fall 2006 November 13nd Name: _____________________________ SSN: ______________________ I have neither given nor received information during the exam. 1 Signature__________________________ Date______________________________ 1. (10 points) Looking at the following instruction sequence, use arrows to indicate the type of data hazards, which will arise without forwarding of any kind. Indicate those that can be completely overcome by forwarding and those that cannot. Do not alter the instruction sequence!!! add $10,$9,$1 LW $8, 60($10) SW $1, 50($8) add $1,$2,$8 sub $4,$5,$1 2. ( 5 points) Modify the following sequence of instructions using a delayed branch to eliminate as many stalls as possible. We don’t know if the branch is taken or not. State your assumptions if any. add $17, $3, $2 sub $5, $6, $2 add $4, $7, $2 beq $17, $4, label1 2 3. (10 points) Consider this simple single-cycle ISA. This looks a little like MIPS--but it is not MIPS. • The machine has 16-bit words. All instructions are 16-bits. There are only 4 registers. • There are only 2 instruction formats, shown below. We ignore load/store, branches here. • The datapath (without any control logic) is shown below, in its entirety. This datapath works fine for MIPS-style arithmetic like: ADD R3,R2,R1 or ADDI R3,R1,5.But we want to add this new I-format instruction: MAI Rd,Rs,imm which does this: Rd = Rd +Rs * imm multiply (Rs * imm), then add it to Rd, write back into Rd. Do this: 3 • Explain in a couple of sentences if this new instruction cannot be executed in one clock cycle. • Modify the datapath so that it can do the MAI instruction. You can add any ALUs, MUXs, busses, etc., that you need. Don’t worry about control logic. You can draw on the existing figure, or just redraw (label clearly!) the parts that need to be changed. Hints: • Make sure you can get the data you want into/out of the registers. Make sure you can do the “+” and the “*” parts of the MAI. Explain: You can add hardware on this figure. 4 If you messed up the previous figure, add hardware on this figure. 5 4. ( 15 points )Let’s now pipeline the machine from Problem 3, using the usual 5stage design. We will add the following to our ISA, and our implementation: 6 • We add one new instruction format, and change the wiring to the PC branch adder (dotted). We pipeline the datapath, and add one forwarding path, and draw the control signal from the ALU to tell whether to take the branch. These are drawn as dotted lines below. Assuming the hardware will detect all hazards and stall as needed, do this: • Show what each instruction in this 2-instruction sequence does in each stage of the pipe 7 (stalls, etc.) ADD R2,R1,R3 BREQ R2,R3, 17 • Tell how many branch delay slots do we need for this datapath? i.e., when do we know whether this branch is taken or not? 5. (10 points) Fill the values for Qs with the following assumptions PC Register Contents à 0x84DC7EF8 Instruction at PC address à add $1,$2,$3 Contents of Register $2 à 0x00100010 8 Contents of Register $3 à 0x0010000C Mem[0x0020001C] = 0x12345678 Instruction [25– 0] 26 Shift left 2 Jump address [31– 0] 28 0 4 Q7 Instruction [31– 26] Q8 PC Instruction [31– 0] Instruction memory Q10a Q9 Instruction [15– 11] Instruction [15– 0] Q15 Add 0 M u x 1 Q14a Q11b Q12 Read register 1 Instruction [20– 16] Q13 Read data 1 Read register 2 Registers Read Write data 2 register 0 M u x 1 Write data Zero ALU ALU result Address Write data Q10b6 1 Sign extend Q11a Read data Data memory 32 ALU control Instruction [5– 0] 000000 00010 00011 00001 00000 010000 9 0 Shift left 2 RegDst Jump Branch MemRead Control MemtoReg ALUOp MemWrite ALUSrc RegWrite Instruction [25– 21] Read address M u x 1 LU Add reAult s Add 1 M u x PC+4 [31– 28] Q14b add $1,$2,$3 1 M u x 0 6. (10 points). Given the architecture diagram as shown below, fill in the values at ? locations in the following finite state machine. There are total of 10 ? in the FSM. The control signals are connected to the outputs control unit. 10 2 M m ry eo access ') SW ''SW 3 A USrcA=1 L A USrcB= ? L A UO = 10 Lp 5 M m ead eR IorD = 1 4 Banch r c m letio op n 8 A U rcA= 1 LS A USrcB= ? L A UOp= ? L PCWiteC n r od PCSo rce = ? u p= (O (O = 'LW) p ' A USrcA= ? L A USrcB= 10 L A UO = ? Lp (Op e p) R-ty = M m ry eo access M m rite eW IorD= ? 7 R-type com letion p Reg st = 1 D RegWite r M mo eg= 0 e tR Wite-b ckstep ra RegD t=0 s RegWite r M moReg=1 et 11 9 (Op='J) ' ') 'SW (Op= Execuio tn 'r W) o p= 'L 6 (O M m ryadd ess eo r co puation mt A USrcA= 0 L A USrcB= ? L A UOp= 00 L 'BE Q') Start Insru tiond co e/ tc ed regster fetch i 1 (O p= Instru tio fetch cn 0 M m ead eR A USrcA= 0 L IorD= 0 IRWite r A USrcB= ? L A UO = 00 Lp PCWite r PCSo rce = 00 u Jum p com letion p PCWite r PCSo rce = ? u 7. Given the following instruction mix, determine number of memory references per instruction for our MIPS machine. Instruction Percentage Loads 10 Stores 20 Branches 15 And 5 Add immediate 10 Jump 15 Subtract 5 Or 20 Hint: You need to know how many times each instruction accesses memory. 12 8. The following problems related to the various characteristics of a cache (10 points) a) for each of the following characteristics of cache, mark if it is a good characteristics or a bad one. 1. decrease miss rate is (good/bad) 2. increasing the miss penalty is (good/bad) 3. increasing the amount of tag storage with respect to the amount of data storage is (good/bad) b) Mark how the characteristics would change if we increased the block size 1. the miss rate, in general (increase/decrease) 2. the miss penalty (increase/decrease) 3. when the block size gets more and more closer to the cache size, the miss rates starts to (increase/decrease) 4. the amount of tag storage with respect to the amount of data storage (increase/decrease) c) Mark how increasing the associativity of the cache would affect its behavior 1. the miss rate (increases/decreases) 2. the hit time generally (increase/decreases) . 13 9. For each of the MIPS code sequences below, indicate if the memory data (data access only) access show temporal locality, spatial locality, both, or neither (by checking the corresponding boxes). (10 points) (1) li $t0, 100_ LOOP: lw $t1, 32767($s0) lw $t2, 0($s0) addi $t0, $t0, -1 bne $t0, zero, LOOP (a) Spatial (b) Temporal (c) Both (d) Neither (2) li $t0, 100 LOOP1: li $t1, 4_ LOOP2: add $t2, $s0, $t1 lb $s1, 0($t2) addi $t1, $t1, -1 bne $t1, zero, LOOP2 addi $t0, $t0, -1 bne $t0, zero, LOOP1 (a) Spatial (b) Temporal (c) Both (d) Neither (3) li $t0, 100_ LOOP: lw $s1, 0($t0) addi $t0, $t0, -1 bne $t0, zero, LOOP (a) Spatial (b) Temporal (c) Both (d) Neither 14 10. Given that the base CPI of a cache system is 2.0. For a clock speed of 1GHz, memory access time is 80cc, a hit rate of 94% in level 1 cache, calculate: i. The memory access time for this system. ii. If we include a 2nd level cache with access time = 15cc and a hit rate of 98%, calculate the memory access time with this new cache included. 15 ...
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This note was uploaded on 09/09/2010 for the course ECE 4436 taught by Professor Staff during the Spring '08 term at University of Houston.

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