lec6 - ECE 3060 VLSI and Advanced Digital Design Lecture 6...

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ECE 3060 Lecture 6–1 ECE 3060 VLSI and Advanced Digital Design Lecture 6 Gate Delay and Logical Effort
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ECE 3060 Lecture 6–2 First Model of Gate Delay This model will be refined shortly
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ECE 3060 Lecture 6–3 Equivalent R The average resistance of a MOSFET is someplace between the linear region, and saturation
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ECE 3060 Lecture 6–4 MOS Capacitor
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ECE 3060 Lecture 6–5 Capacitance Equations Capacitors store charge Q = CV charge is proportional to the voltage on a node The equation can be put in a more useful form i = dQ/dt => i = C*(dV/dt) => (C*dV)/i = t Thus, to change the node’s voltage (e.g., from 0 to 1), the transistor or gate driving that node must charge (up in our example) the capacitance associated with that node. The larger the capacitance, the large the required charge, and the longer it will take to switch the node. Since of a transistor is approximately i dQ dt ------- iC dV C Δ V i Δ t = = = iV R trans
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ECE 3060 Lecture 6–6 Δ t C Δ V i ------------ C Δ V V R trans ⎝⎠ ⎛⎞ ------------------ R trans C = = =
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ECE 3060 Lecture 6–7 Calculating R and C pFET vs. nFET Mobility ( μ ) of electrons twice mobility of holes pFET resistance is twice nFET resistance Series and Parallel Configurations Series resistances add Parallel: worst case is one transistor on Transistor Sizing Resistance Inversely Proportional to W / L Gate Capacitance Proportional to W x L
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ECE 3060 Lecture 6–8 Symmetric Rise/fall? Make , but then gate capacitance increased β n β p = 1 1 -- 1 1 1 1 1 1 2 1 2 1 1 1 1 1
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ECE 3060 Lecture 6–9 Tau Metric We can normalize delay to technology independent
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lec6 - ECE 3060 VLSI and Advanced Digital Design Lecture 6...

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