lec9 - ECE 3060 VLSI and Advanced Digital Design Lecture 9...

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ECE 3060 VLSI and Advanced Digital Design Lecture 9 Logical Effort: Asymmetric Gates, Bundles
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ECE 3060 Lecture 9–2 More Notation It turns out, we do not need to fix p-fets to be twice as wide as n-fets (See chapter 7) Let be defined as the ratio of p-fet width to n-fet width in an inverter. Then LE can be defined in terms of . So far we have defined LE specifically on a per input basis. The text introduces additional terms: The logical effort per bundle is the sum of the logical efforts of related signals Example: A signal and its complement are both inputs to a gate. This input bundle is called . Total logical effort is the sum of the logical effort of all inputs to a gate. γ γ ss s *
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ECE 3060 Lecture 9–3 Asymmetric Gates Consider and AOI21: Note that input has lower logical effort (5/3 vs 2) than
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lec9 - ECE 3060 VLSI and Advanced Digital Design Lecture 9...

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