# lec9 - ECE 3060 VLSI and Advanced Digital Design Lecture 9...

This preview shows pages 1–7. Sign up to view the full content.

ECE 3060 VLSI and Advanced Digital Design Lecture 9 Logical Effort: Asymmetric Gates, Bundles

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
ECE 3060 Lecture 9–2 More Notation It turns out, we do not need to fix p-fets to be twice as wide as n-fets (See chapter 7) Let be defined as the ratio of p-fet width to n-fet width in an inverter. Then LE can be defined in terms of . So far we have defined LE specifically on a per input basis. The text introduces additional terms: The logical effort per bundle is the sum of the logical efforts of related signals Example: A signal and its complement are both inputs to a gate. This input bundle is called . Total logical effort is the sum of the logical effort of all inputs to a gate. γ γ ss s *
ECE 3060 Lecture 9–3 Asymmetric Gates Consider and AOI21: Note that input has lower logical effort (5/3 vs 2) than

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 7

lec9 - ECE 3060 VLSI and Advanced Digital Design Lecture 9...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online