lec13 - ECE 3060 VLSI and Advanced Digital Design Lecture...

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ECE 3060 VLSI and Advanced Digital Design Lecture 13 Datapath1: ALUs and Adders
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ECE 3060 Datapath1–2 Datapath Floorplan Busses run through cells Pitch is matched Vdd and Gnd are run horizontally Current draw on Vdd and Gnd is spread in time to minimize spiking
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ECE 3060 Datapath1–3 Example Chip Floorplan
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ECE 3060 Datapath1–4 Transmission Gate Mux I0 I1 I2 I3 Out I0 I1 I2 I3 S0 S1 S0 S1 S0 S1 S0 S1 Note: Two t-gates in series do not need the internal connection between p-fet and n-fet
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ECE 3060 Datapath1–5 Function Block 4x1 multiplexor can implement any function of two variables Simply place the truth table for F on the inputs of the mux. The operands A and B will select the correct value of the function A B F S 4
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ECE 3060 Datapath1–6 Adder Cells Above equations may be implemented as complex gates These equations may be manipulated to yield: SUM ABC ⊕⊕ = CAB AB + () + + = CARRY AB AC BC ++ = C A B + + = SUM A B C CARRY + =
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ECE 3060 Datapath1–7 Adder Layout
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ECE 3060 Datapath1–8
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lec13 - ECE 3060 VLSI and Advanced Digital Design Lecture...

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