# lec15 - ECE 3060 VLSI and Advanced Digital Design Lecture...

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ECE 3060 VLSI and Advanced Digital Design Lecture 15 Multiple-Level Logic Minimization

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Outline • Multi-level circuit representations • Minimization methods – goals: area, delay, power – algorithms: algebraic, boolean – rule-based methods • Examples of transformations • Boolean and algebraic models Disclaimer: lecture notes based on originals by Giovanni De Micheli
Motivation • Multiple level networks – Semi-custom libraries – Advantages of gates versus macros (PLA) 8 more flexible 8 better performance •might want to minimize certain paths • Applicable to a variety of designs

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Circuit modeling • Logic network – interconnection of logic functions – hybrid structural/behavioral model • Bound (mapped) gates – interconnection of logic gates – structural model
Example of a bound network

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Logic equations of example 8 p = ce + de 8 q = a + b 8 r = p + a’ 8 s = r + b’ 8 t = ac + ad + bc + bd + e 8 u = q’c + qc’ + qc 8 v = a’d + bd + c’d + ae’ 8 w = v 8 x = s 8 y = t 8 z = u
Example of network

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Example circuit output function a’d + bd + c’d + ae’ a' + b' + ce + de ac + ad + bc + bd + e a + b + c w x y z
Network optimization • Minimize area (power) estimate – subject to delay constraints • Minimize maximum delay – subject to area (power) constraints • Maximize testability • Minimize power

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Estimation • Area: – number of literals 8 in MOS, # literals = # poly strips – number of functions/gates • Delay: – number of stages 8 most often used metric – refined gate delay models – sensitizable paths 8 paths for which there are conditions under which a signal propagates through the path
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## This note was uploaded on 09/11/2010 for the course ECE 3060 taught by Professor Shimmel during the Fall '07 term at Georgia Tech.

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lec15 - ECE 3060 VLSI and Advanced Digital Design Lecture...

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