lec4 - ECE 3060 VLSI and Advanced Digital Design Lecture 4...

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ECE 3060 VLSI and Advanced Digital Design Lecture 4 Layout Design & Tools
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ECE 3060 Lecture 3–7 CMOS Layers “Standard” n -Well Process Active (Diffusion) Polysilicon Metal 1, Metal 2, Metal3 Poly Cut (connects metal 1 to polysilicon) Active Cut (connects metal 1 to active) Via (connects metal 2 to metal 1) Overglass Cut (facilitates off-chip connections) n Well n Select (used with active to create n -type diffusion) p Select (used with active to create p -type diffusion) p -well, twin tub, etc. use slightly different layers
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ECE 3060 Lecture 3–8 Well, Active, and Select Layout p-select n-select Active Active n- field oxide p+ n+ p- (substrate) Layout Cross section
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ECE 3060 Lecture 3–9 Transistor Layout p-select n-select Active Active n- field oxide p+ n+ p- (substrate) Layout Cross section p-fet n-fet thin oxide
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ECE 3060 Lecture 3–10 Wiring and Contact Layout
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ECE 3060 Lecture 3–12 Substrate and Well Contacts Properties Set Well and Substrate Voltages to Vdd and Gnd Prevent Forward Biasing and Latch-Up Must Be at Least One per Well Should Be Placed Regularly
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ECE 3060 Lecture 3–13 Design Rules Minimum Separation [A] Intralayer (all layers) Interlayer (active to poly/well/select) From Transistor Minimum Width (all layers) [B] Minimum Overlap [C] Past Transistor (poly, active) Around Contact Cut (all contacted layers) Around Active (well, select) Exact Size (contact cuts) [D]
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Lambda Rules for TSMC .18u
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This note was uploaded on 09/11/2010 for the course ECE 3060 taught by Professor Shimmel during the Fall '07 term at Georgia Tech.

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lec4 - ECE 3060 VLSI and Advanced Digital Design Lecture 4...

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