lec17 - ECE 3060 VLSI and Advanced Digital Design Lecture...

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ECE 3060 VLSI and Advanced Digital Design Lecture 17 Sequential System Design
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ECE 3060 Lecture 17–2 Setup and Hold Time Clock Data Setup Hold
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ECE 3060 Lecture 17–3 Timing Assertions A signal is (valid ) if it is stable from before to after the falling edge of . A signal is (stable ) if it is stable from before the rising edge to after the falling edge of . A signal is (qualified ) if is formed from a sig- nal which is ANDed with . V φ n φ φ S φ φ φ φ 2 φ 1 V φ 1 S φ 2 Q φ 1 Q φ φ φ φ
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ECE 3060 Lecture 17–4 Signal Hierarchy Relationships between signal assertions can be repre- sented graphically S φ 1 S φ 2 V φ 1 S φ 2 S φ 1 V φ 2 S φ 1 V φ 1 V φ 2 S φ 2 V φ 2 V φ 1 Q φ 2 Q φ 1
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ECE 3060 Lecture 17–5 How to use Assertions A latch is clocked by clock qualified signal Weakest input assertion is Assert strongest output assertion possible V φ n
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ECE 3060 Lecture 17–6 Sequential Control Functionality Generates Control Signals to Datapath (Registers and ALU) Designed as a Finite State Machine Cycles through States as a Function of Input C L Storage Outputs Inputs V φ 2 S φ 1 () φ 1
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This note was uploaded on 09/11/2010 for the course ECE 3060 taught by Professor Shimmel during the Fall '07 term at Georgia Tech.

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lec17 - ECE 3060 VLSI and Advanced Digital Design Lecture...

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