AND8001-D - AND8001/D Odd Number Divide By Counters With 50...

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Semiconductor Components Industries, LLC, 1999 October, 1999 – Rev. 0 1 Publication Order Number: AND8001/D AND8001/D Odd Number Divide By Counters With 50% Outputs and Synchronous Clocks Prepared by: Cleon Petty and Paul Shockman Product Applications ON Semiconductor The application inquiries handled by the Product Applications gives opportunities to solve customer needs with new ideas and learn of ways the customer has used our devices in new applications. A couple of these calls lead to techniques of designing odd number counters with synchronous clocks and 50% outputs. The first technique requires a differential clock, that has a 50% duty cycle, a extra Flip Flop, and a gate to allow Odd integers, such as 3, 5, 7, 9, to have 50% duty cycle outputs and a synchronous clock. The frequency of operations is limited by Tpd of the driving FF, Setup, and Hold of the extra FF, and the times cannot exceed one half on the incoming clock cycle time. The design begins with producing a odd number counter (Divide By 3 for this discussion) by any means one wishes and add a flip flop, and a couple of gates to produce the desired function. Karnaugh maps usually produce counters that are lockup immune. Example: Specify, Divide By 3, 50% duty cycle on the output Synchronous clocking 50% duty cycle clock in Using D type Flop flips and karnaugh maps we find; Ad = A*B* and Bd = A (Note: * indicates BAR function) Figure 1 shows schematic and timing of such a design. Figure 1. Q Q D C Q Q D C Divide By 3 AB http://onsemi.com APPLICATION NOTE
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AND8001/D http://onsemi.com 2 Using the technique, we add a gate on the clock to get differential Clock and Clock bar, a flip flop that triggers on the Clock Bar rising edge (Clock Neg.) to shift the output of ”B” by 90 degrees and a gate to AND/OR two FF output to produce the 50% output. We get Figure 2, a Divide By 3 that clocks synchronously with 50% output duty cycle. Figure 2. Q Q D C Q Q D C Divide By 3 W/50% out Q Q D C 50% Out Clk in ABC Clk A Q B Q C Q OUT The Max frequency of the configuration (figure 2) is calculated as Clock input freq./2 = Tpd of FF ”B” + Setup of ”C” + Hold of ”C”. Example: Tpd = 1Ns, Setup = !NS and Hold time = 0Ns. with these numbers the Max Frequency the configuration can expect is; Cycle time = 2*(1 + 1)Ns or 4 Ns that converts to 250MHZ.
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AND8001-D - AND8001/D Odd Number Divide By Counters With 50...

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