HW6_solutions_rev

# HW6_solutions_rev - Homework 6 1 Problem(a Using the...

This preview shows page 1. Sign up to view the full content.

This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Homework 6 1. Problem: (a) Using the ﬁgures on pages 133 and 134 of the Lecture Notes, Part II, as a guide, sketch the band diagram of an MOS capacitor with an n-type Si substrate in i) accumulation, ii) at ﬂat band condition, and iii) at the onset of strong inversion (that is, ψs = 2ψB ). Assume an Al gate with electron aﬃnity eφM = 3.0 eV, use for Si the work-function eχ = 3.2 eV, and assume the n-type substrate to be doped with ND = 3 × 1017 donors/cm3. (b) What is the value of the ﬂatband voltage VF B and of the threshold voltage VT 0 (see Eq. (247) of the Notes, Part III)? (c) What is the value of the depletion capacitance CD at the onset of strong inversion? Solution: (a) See the ﬁgures. (b): Looking at the ﬁrst ﬁgure, the distance between the metal Fermi level and the vacuum level (the topmost dashed horizontal line) is given by: |VF B | + eφM = |VF B | + 3.0 eV . Similarly, the distance between the Si Fermi level and the vacuum level will be given by: (1) eχ + Ei − ψB = 3.2 + 0.55 − 0.435 eV = 3.315 eV , (2) ECE344 Fall 2009 1 3.5 3.0 METAL INSULATOR SEMICONDUCTOR ELECTRON POTENTIAL ENERGY (eV) 2.5 2.0 1.5 1.0 0.5 0.0 EF,M –0.5 –1.0 –1.5 –2.0 –150 –100 EV eVFB e ψB EC EF,S Ei e φM eχ FLAT BANDS –50 0 DISTANCE (nm) 50 100 ECE344 Fall 2009 2 METAL INSULATOR SEMICONDUCTOR METAL INSULATOR SEMICONDUCTOR EC EF,S Ei EV eVG > 0 EF,M eVG < 0 EC EF,S Ei EV EF,M ACCUMULATION INVERSION where ψB = kB T ln(ND /ni ) is the distance between the Fermi level and the intrinsic level Ei. From Eqns. (1) and (2), noticing that VF B must be negative (since it raises the potential energy for electrons in the gate), we have VF B = - 0.315 V. Finally, the threshold voltage is given by Eq. (247) of the Notes with γ = (2 S i eND )1/2 (with ND replacing NA since we are dealing with an n-type substrate. Thus, using Cox = ox /tox and tox = 5 nm (from Problem 2): 11.7 × 8.85 × 10−12 F/m Cox = = 6.9 × 10−3F/m2 . 5 × 10−9m ECE344 Fall 2009 (3) 3 To compute the body-factor γ let’s convert the doping density to m−3 : (2 × 1.6 × 10−19 × 11.7 × 8.85 × 10−12 × 3 × 1023 )1/2 9.22 × 10−4 γ= ≈ = 0.134 V1/2 −4 −3 6.9 × 10 6.9 × 10 (4) Thus: 1/2 VT 0 = VF B + 2ψB + γ (2ψB ) ≈ −0.315 + 0.87 + 0.125 = 0.68 V (5) (c) The depletion capacitance is given by: , (6) WD where WD = [2 S i ψs /(eND )]1/2 is the depletion width. The minimum capacitance is obtained when the depletion width reaches its maximum value, for ψs = 2ψB . Using the value for ψB calculated above we have: CD = WD,max = So: Si 4 S i ψB eND 1/2 ≈ 61.3 nm . (7) 11.7 × 8.85 × 10−12F/m CD,min = = 1.7 × 10−7 F/cm2 6.13 × 10−8m (8) 2. Problem: Assuming an oxide thickness tox of 5 nm and a gate area of 100 µm2 , sketch the capacitance-voltage (C − V ) characteristics of the MOS capacitor of problem 1, as in the ﬁgure at page 140 of the Lecture Notes. Recall that this capacitor is on an n-type substrate! Solution: See the following ﬁgure: ECE344 Fall 2009 4 Cox Cox GATE CAPACITANCE low frequency VFB Cmin high–frequency GATE VOLTAGE 3. Problem: Consider a Si nMOSFET with the following parameters: substrate doping (p-type): NA = 5 × 1016 cm−3 channel length L = 0.5 µm gate width W = 5 µm electron mobility µn = 600 cm2 /Vs oxide thickness tox = 15 nm ﬂatband voltage VF B = 0. Using the simpliﬁed model of the Lecture Notes, pages 159-162, especially Eq. (255), plot as accurately as you Note that we have already calculated Cox ≈ 6.9 × 10−3 F/m2 and CD ≈ 1.7 × 10−3 F/m2 . Since the area of the capacitor is 100 µm2 = 10−6cm−2 , we have Cox ≈ 0.69 pF, CD ≈ 0.17 pF, so that the minimum capacitance at high frequency in inversion will be Cmin = 1/(1/Cox + 1/CD ) ≈ 0.14 pF. ECE344 Fall 2009 5 can the ID − VD characteristics of the device assuming that the source contact is grounded (that is, VS =0). More speciﬁcally, plot ID -vs-VD for VG − VT 0 = 0.0, 0.5, 1.0. 1.5, and 2.0 V for VD ranging from 0 to 5 V. Indicate as best as you can the separation between the linear and saturated region by computing VD,sat for the various values of VG − VT 0 . Also indicate the value of the threshold voltage VT 0 . Solution: The ﬁgure below shows the drain current as a function of drain bias in four curves (black, solid lines) parametrized by the gate overdrive VG − VT 0 . Note that VT 0 = 1.27 V and n = 1.32. The parabola indicated by a dashed black line is given by the expression: Wn 2 ID = µ Cox (9) V, L2 D and it separates the linear (left) from the saturated region (right). When VD exceeds VD,sat – so, at the right of the dashed parabola – Eq. (255) is not valid, as explained at page 160, immediately after Eq. (255), because the channel is pinched oﬀ. Many of you, especially those who have employed a computer to evaluate numerically the current, have forgotten this fact and have used Eq. (255) also when VD > VD,sat , getting negative values for the current. Not good... ECE344 Fall 2009 6 400 VT0 = 1.27 V 300 VG–VT0=2.0 ID (µA/m) 200 VG–VT0=2.0 1.5 1.5 1.0 0.5 1.0 0.5 1.5 2.0 100 0 0.0 0.5 1.0 VD (V) 4. Problem: As in problem 3 above, plot the same ID − VD characteristics, but now account for the degradation of the electron mobility with increasing VG via Eq. (298) of the Lecture Notes. To do this, just replace µn in Eq. (255) with µef f given by Eq. (298). Use a value of K such that KCox/(2 s ) = 0.5 V−1. Solution: The drain current is shown in the ﬁgure above by red dashed lines. ECE344 Fall 2009 7 5. Problem: Consider a Si nMOSFET with the following parameters: substrate doping (p-type): NA = 5 × 1016 cm−3 channel length L = 1.0 µm gate width W = 10 µm electron mobility µn = 600 cm2 /Vs oxide thickness tox = 4 nm threshold voltage VT 0 = 1 V. Using, as in the previous problem, the simpliﬁed model of the Lecture Notes, pages 159-162, especially Eq. (255), calculate the width of a similar pMOSFET giving the same saturated current for the same gate overdrive (that is, at the same value of |VG − VT 0 |). Assume for the hole mobility a value of µp = 200 cm2 /Vs. If you wish, you may assume also for the threshold voltage of the pMOSFET the value of -1 V. Recall that in dealing with the pFET all polarities (VD and VG ) are switched. Do you really need to know the entire set of parameters characterizing the devices in order to reach your answer? Solution: No, you don’t. Since the threshold voltage has the same magnitude (just of opposite polarity), the only reason why the two currents (for the n and p FETs) diﬀer at a given gate overdrive is due to the diﬀerent mobilities for the two devices. Since the hole mobility is three times smaller than the electron mobility, the p-channel FET must be three times wider, that is W = 30 µm, in order to carry the same current. ECE344 Fall 2009 8 ...
View Full Document

## This note was uploaded on 09/13/2010 for the course ECE ECE344 taught by Professor Polizinni during the Spring '10 term at University of Massachusetts Boston.

Ask a homework question - tutors are online