EE357-HW2_solutions-Nazarian-Fall09

EE357-HW2_solutions-Nazarian-Fall09 - EE 357 Homework 2...

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1 EE 357 Homework 2 Solutions Fall 2009 Nazarian Assigned Friday, Sep. 18 Due: Friday, Sep. 25 at 1pm (RTH109) Score: ________ Instruction Set Architecture 1. a. T / F : Instruction Set Architecture must define HW implementation details like clock speed. b. T / F : Generally speaking, an ISA using one-operand instructions will require fewer instructions to perform a specified operation than a 2 or 3-operand format. c. T / F : Instruction Set Architecture really cannot affect the performance of a program’s execution? 2. Processor Address Bus Width Maximum Amount of Mem. Intel Pentium 4 36 ___ 64 ____ K / M / G / T Intel 80486 32 ___ 4 ____ K / M / G / T Intel 8086 20 ___ 1 ____ K / M / G / T
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2 Dealing with Data Sizes 3. Operation R/W of Mem.? D0 = ?? M[0x20030004]=?? .data .space 4 .text move.l #0x01234567,D0 move.l #0xfedcba98, D1 a: move.l D1,0x20003004 R/ W 0x01234567 0xfedcba98 b: move.b 0x20003004,D0 R /W 0x012345fe 0xfedcba98 c: move.w D0,0x20003006 R/ W 0x012345fe 0xfedc45fe d:
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This note was uploaded on 09/14/2010 for the course EE 357 at USC.

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EE357-HW2_solutions-Nazarian-Fall09 - EE 357 Homework 2...

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