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EE357-HW2_solutions-Nazarian-Fall09

EE357-HW2_solutions-Nazarian-Fall09 - EE 357 Homework 2...

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1 EE 357 Homework 2 Solutions Fall 2009 Nazarian Assigned Friday, Sep. 18 Due: Friday, Sep. 25 at 1pm (RTH109) Score: ________ Instruction Set Architecture 1. a. T / F : Instruction Set Architecture must define HW implementation details like clock speed. b. T / F : Generally speaking, an ISA using one-operand instructions will require fewer instructions to perform a specified operation than a 2 or 3-operand format. c. T / F : Instruction Set Architecture really cannot affect the performance of a program’s execution? 2. Processor Address Bus Width Maximum Amount of Mem. Intel Pentium 4 36 ___ 64 ____ K / M / G / T Intel 80486 32 ___ 4 ____ K / M / G / T Intel 8086 20 ___ 1 ____ K / M / G / T
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