EE357-HW2-Nazarian-Fall09

EE357-HW2-Nazarian-Fall09 - EE 357 Homework 2 Fall 2009...

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1 of 5 EE 357 Homework 2 Fall 2009 Nazarian Name: ___________________________________________ Assigned Friday, Sep. 18 Due: Friday, Sep. 25 at 1pm (RTH109) Score: ________ Instruction Set Architecture 1. (3 pts.) Enter ‘T’ or ‘F’ for each question below. a. T / F : Instruction Set Architecture must define HW implementation details like clock speed. b. T / F : Generally speaking, an ISA using one-operand instructions will require fewer instructions to perform a specified operation than a 2 or 3-operand format. c. T / F : Instruction Set Architecture really cannot affect the performance of a program’s execution? 2. (6 pts.) Given the address bus widths of the following processors, state the approximate size of the address space in bytes. Submission Instructions : Enter a decimal number in the first blank and then K, M, G, or T in the second blank for each question. Processor Address Bus Width Maximum Amount of Mem. Intel Pentium 4 36 _______ K / M / G / T Intel 80486 32 _______ K / M / G / T Intel 8086 20 _______ K / M / G / T
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2 of 5 Dealing with Data Sizes 3. (35 pts.) Enter the following assembly program in Codewarrior and step through each instruction viewing the D0 register contents and memory at address 0x20003004. Ensure you understand the results of each instruction. Instructions : For each line labeled a: through g:, enter R or W in the first blank, followed by the 32-bit hexadecimal value of D0 (including the ‘0x’ prefix) in the second blank, and then the 32-bit hexadecimal value of the indicated memory location (including the ‘0x’ prefix). Operation
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EE357-HW2-Nazarian-Fall09 - EE 357 Homework 2 Fall 2009...

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