EE357-HW4-Nazarian-Fall09

EE357-HW4-Nazarian-Fall09 - EE 357 Homework 4 Fall 2009...

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1 EE 357 Homework 4 Fall 2009 Nazarian Name: ___________________________________________ Assigned Tuesday, Nov. 3 Due: Thursday, Nov. 12 in class (RTH 105) Score: ________ 1) (12 pts.) A certain memory controller connects a processor with a 32-bit address bus (A31-A0) and 64-bit data bus to a memory system consisting of 2 SIMM’s (ranks). Each SIMM consists of (8) 64M x 8-bit chips (i.e. each addressable unit/column grouping is 8-bits). Each of these chips has 2 banks with 8K rows each. In the table below, show the address bit ranges that will be used for each portion. Do so by writing in An – Am where n and m are the most and least significant bit indexes for that range (e.g. A5-A2). Unused MSBs Rank Row Bank Column Unused (64-bit data bus) 2) (12 pts.) A certain memory controller connects a processor with a 36-bit address bus (A35- A0) and 32-bit data bus to a memory system consisting of 2 DIMM’s (4 ranks). Each DIMM consists of (8) 128M x 4-bit chips (i.e. each addressable unit/column grouping is 4-bits). Each of these chips has 4 banks with 1024 (1K) rows each. In the table below, show the address bit ranges that will be used for each portion. Do so by writing in An – Am where n and m are the most and least significant bit indexes for that range (e.g. A5-A2).
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This note was uploaded on 09/14/2010 for the course EE 357 at USC.

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EE357-HW4-Nazarian-Fall09 - EE 357 Homework 4 Fall 2009...

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