Unit2-MulDiv-EE357-Nazarian-Fall09

Unit2-MulDiv-EE357-Nazarian-Fall09 - University University...

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University of Southern California Viterbi School of Engineering EE357 asic Organization of Computer Systems Basic Organization of Computer Systems ultiplication and Division Techniques Multiplication and Division Techniques References: 1) Textbook ) ark Redekopp’s slide series Shahin Nazarian Fall 2009 2) Mark Redekopp s slide series
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Concepts & Skills Concepts Signed and Unsigned multiplication process Sequential vs. combinational adder design Optimizations to multipliers Skills Add & Shift (Sequential) Multiplication dd & Sh ft (Sequent al) Mult pl cat on method Signed Multiplication with Booth’s algorithm and Bit-Pair Recoding Shahin Nazarian/EE357/Fall 2009 2
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Arithmetic Review erform the following operation and state Perform the following operation and state whether overflow occurred (for both signed and/or unsigned case) 57FD 5 7FD If unsigned verflow - 936B 6 C94 + 1 92 Overflow Cout = 1 If signed C 492 Overflow p + p = n Shahin Nazarian/EE357/Fall 2009 3
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Add and Shift Method (Sequential) MULTIPLICATION an Sh ft M tho (S qu nt a ) Booth’s Coding and Bit-Pair Recoding TECHNIQUES Shahin Nazarian/EE357/Fall 2009 4
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Unsigned Multiplication Review Same rules as decimal multiplication ultiply each bit of Q by M shifting as you go Multiply each bit of Q by M shifting as you go An m-bit * n-bit mult. produces an m+n bit result (i.e. n-bit * n-bit produces 2*n bit result) Notice each partial product is a shifted copy of M or 0 (zero) 010 (Multiplicand) 1010 * 1011 1010 M (Multiplicand) Q (Multiplier) 1010_ 0000__ + 1010 PP(Partial Products) Shahin Nazarian/EE357/Fall 2009 01101110 P (Product) 5
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Multiplication Techniques A multiplier unit can be Purely Combinational: Each partial product is produced in parallel and fed into an array of adders to generate the product Sequential and Combinational: Produce and add one partial product at a time (per cycle) Shahin Nazarian/EE357/Fall 2009 6
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Combinational Multiplier artial Product (PP Generation Partial Product (PP i ) Generation Multiply Q[i] * M if Q[i]=0 => PP i = 0 if Q[i]=1 => PP i = M AND gates can be used to generate each partial product M[3] M[2] M[1] M[0] M[3] M[2] M[1] M[0] Q[ i]=0 if… Q[ i]=1 if… 0 0 0 01 1 1 1 Shahin Nazarian/EE357/Fall 2009 0 0 0 0 M[3] M[2] M[1] M[0] 7
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Combinational Multiplier Partial Products must be added together ombinational multipliers are generally slow Combinational multipliers are generally slow because of the propagation delay through the adders propagation delay is proportional to the number of partial products (i.e. number of its of input) and the width of each adder bits of input) and the width of each adder Shahin Nazarian/EE357/Fall 2009 8
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Adder Propagation Delay 1111 0001 + 0001 XY Ci Co Ci Co FA Ci Co Ci Co 0 0 0 0 S S S S Shahin Nazarian/EE357/Fall 2009 9
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Adder Propagation Delay 1111 0001 + 0001 1111 1 0 0 0 XY Ci Co Ci Co FA Ci Co Ci Co 0 0 0 0 S S S S Shahin Nazarian/EE357/Fall 2009 10
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Adder Propagation Delay 1111 0001 1111 1 0 0 0 + 0001 XY Ci Co Ci Co FA Ci Co Ci Co 0 1 0 0 0 S S S S 0 1 1 1 Shahin Nazarian/EE357/Fall 2009 11
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Adder Propagation Delay 1111 0001 1111 1 0 0 0 + 0001 XY Ci Co Ci Co FA Ci Co Ci Co 0 1 1 0 0 S S S S 0 0 1 1 Shahin Nazarian/EE357/Fall 2009 12
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Unit2-MulDiv-EE357-Nazarian-Fall09 - University University...

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