Unit7-Cmp&Branch-EE357-Nazarian-Fall09

Unit7-Cmp&Branch-EE357-Nazarian-Fall09 - University...

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University of Southern California Viterbi School of Engineering EE357 asic Organization of Computer Systems Basic Organization of Computer Systems ompare and Branch Instructions Compare and Branch Instructions Branch Translation References: 1) Textbook 2) Mark Redekopp’s slide series Shahin Nazarian Fall 2009 3) Freescale documents on CF
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Condition Codes (Flags) Processor performs tests on the result of each instruction 5 tests w/ results stored as 1=true/0=false in SR (Status Reg.) X = eXtended Flag Used for Extended Precision Arithmetic Usually set the same as the C flag N = Negative Flag Tests if the result is negative ust a copy of the MSB of result Just a copy of the MSB of result Z = Zero Flag Tests if the result is equal to 0 V = 2’s complement oVerflow Flag Set if p+p=n or n+n=p C = Carry Flag (Unsigned Overflow Flag) Shahin Nazarian/EE357/Fall 2009 2 Set if (Cout=1 and Add op.) or (Cout=0 and Sub. Op)
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Instructions & Condition Codes Different instructions affect the condition codes differently Refer to instruction data sheets for instruction-specific effects eneral effects guidelines are as follows General effects guidelines are as follows XNZV C MOVE - * * 0 0 A D D / S U B / C M P ***** LSx/ASx * * * 0 * Logic - * * 0 0 B r a n c h e s / J u m p s ----- Shahin Nazarian/EE357/Fall 2009 3 * = Set according to traditional or instruction-specific definition - = Unaffected (unchanged from previous value) 0 = Cleared to 0
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Condition Code Examples Instruction D0 X N Z V C MOVE.L #0x7fffffff,D0 7fffffff - 0 0 0 0 •MOVE by definition leaves X unaffected and V = C = 0 •0x7fffffff is NOT negative (N=0) •0x7fffffff is NOT equal to 0 (Z=0) Shahin Nazarian/EE357/Fall 2009 4
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Condition Code Examples Instruction D0 X N Z V C MOVE.L #0x7fffffff,D0 7fffffff - 0 0 0 0 DDI L #0x80000001 D0 0000000 ADDI.L #0x80000001,D0 00000000 1 0 1 0 1 •ADD instruc. & C out = 1 so X = C = 1 ffffff •Result is NOT negative (N=0) •Result is equal to zero (Z=1) 7fffffff + 80000001 Result = 00000000 Shahin Nazarian/EE357/Fall 2009 5 •P + N can’t yield 2’s comp. overflow (V=0)
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Condition Code Examples Instruction D0 X N Z V C MOVE.L #0x7fffffff,D0 7fffffff - 0 0 0 0 DDI L #0x80000001 D0 0000000 ADDI.L #0x80000001,D0 00000000 1 0 1 0 1 SUBI.L #0x80000000,D0 80000000 1 1 0 1 1 • SUB instruc. & C out = 0 so X = C = 1 0000000 • Result is negative (N=1) • Result is NOT equal to zero (Z=1) 00000000 7fffffff + 1 esult = 0000000 Shahin Nazarian/EE357/Fall 2009 6 • P + P = N means 2’s comp. overflow (V=1) Result 80000000
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LSx and Asx Instructions C and X flags are set with the last bit shifted out N and Z are set normally V = 0 Right Logical/Arithmetic Shift C,X C,X Left Logical/Arithmetic Shift 0 0 1 1 0 0 0 1 0 1 C,X Initial Value 1 1 0 0 0 101 C,X 0 0 0 1 1 0 0 0 1 Shifted by 3- its 0 0 1 0 1 0 0 0 0 Shahin Nazarian/EE357/Fall 2009 7 bits C & X flag = Last bit shifted out
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LSL and LSR Instructions D2 X N Z V C MOVE.L #0xF0000003,D2 MOVE.L #3,D3 F000 0003 - 1 0 0 0 - 0 0 0 0 1111 0000 0000 0000 0000 0000 0000 0011 LSR.L #1,D2 1 0 0 0 1 1 Right Shift by 1-bit 0111 1000 0000 0000 0000 0000 0000 0001 C,X LSL.L D3,D2 Left Shift by 3-bits 1 1 0 0 1 C,X 1100 0000 0000 0000 0000 0000 0000 1000 D2 = 0x78000001 1 D2 = 0xC0000008 Shahin Nazarian/EE357/Fall 2009 8
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ASL and ASR Instructions D2 X N Z V C MOVE.L #0x80000003,D2 MOVE.L #1,D3 8000 0003 - 1 0 0 0 - 0
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This note was uploaded on 09/14/2010 for the course EE 357 at USC.

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Unit7-Cmp&Branch-EE357-Nazarian-Fall09 - University...

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