Unit12-Interrupts&Timer-EE357-Nazarian-Fall09

Unit12-Interrupts&Timer-EE357-Nazarian-Fall09 -...

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University of Southern California Viterbi School of Engineering EE357 asic Organization of Computer Systems Basic Organization of Computer Systems nterrupts Interrupts Timers References: 1) Textbook 2) Mark Redekopp’s slide series Shahin Nazarian Fall 2009 3) Freescale documents on CF
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Coldfire / M68K Interrupts Coldfire interrupt architecture is based on original M68K 3-bit input ( IPL [2:0]) indicating interrupt requests/priorities (IPL stands for Interrupt Priority Level ) 000 = No interrupt 001-111 = Device 1-7 requesting interrupt Processor Core bits I/O Source Encoder 1 Shahin Nazarian/EE357/Fall 2009 2 IP L I/O Source I/O Source 3 7
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Masking Interrupts in the Processor Core May be times when we want the processor to execute important code and ignore (mask) terrupts interrupts I-bits in SR accomplish this Interrupt n will be ignored if n I-bits, with the exception of n=7 which can never be ignored 0 0 1 0 101 000 1 0 1 0 1 SR: I-bits=5: Ignore 0 TS I - b i t s X N Z V C interrupts [1-5] M Shahin Nazarian/EE357/Fall 2009 3 0 0 1 000 000 1 0 1 0 1 SR: I - b i t s X N Z V C I-bits=0: Enable all interrupts 0 0 M
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Non-Maskable Interrupt (NMI) - its = 7 would normally mean ignore all I bits 7 would normally mean ignore all interrupts (n will always be I) oldfire defines NT 7 =7) on- askable Coldfire defines INT 7 (n 7) non maskable Cannot be ignored even if I = 7 MI on askable Interrupt] is a safe NMI [Non-Maskable Interrupt] is a safe guard to ensure some device can cause an interrupt no matter what Shahin Nazarian/EE357/Fall 2009 4
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Priority Inversion Problem Normally, higher priority interrupt should be handled before lower priority interrupts Example: INT 5 should be processed before INT 3 Priority inversion occurs when a lower priority interrupt takes place during handling of a higher priority interrupt Shahin Nazarian/EE357/Fall 2009 5
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Priority Inversion Problem .text MAIN --- --- (INT 5) --- .text ISR5 --- (INT 3) --- --- .text ISR3 --- --- --- --- --- --- INT 3 interrupts ISR 5 and in effect INT 3 is handled before ISR 5 thus inverting the normal priority scheme ORG $1000 MAIN --- --- (INT 5) ORG $1100 ISR5 --- (INT 3 ignored) --- Set I=5 olution: Raise I its = n --- --- --- ORG $1200 ISR3 --- Restore I Set I=3 Solution: Raise I-bits = n on interrupt n (Raise it to 5 on INT 5 so that INT 3 will be ignored until ISR 5 completes) Shahin Nazarian/EE357/Fall 2009 6 --- --- Restore I
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Interrupt Processing When an interrupt occurs, the CPU finishes the current instruction and then automatically goes through a 6 step process: 1. Ignore interrupt if n I-bits . ake a copy of the SR and Return Address/PC 2. Make a copy of the SR and Return Address/PC 3. Raise I-bits = n 4. Set S=1, T=0 5. Push Return Address and Copy of SR onto stack 6. Load PC with address from Exception Vector Table fter handler finishes and calls RTE After handler finishes and calls RTE, original/copied SR will restore I-bit value Shahin Nazarian/EE357/Fall 2009 7
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This note was uploaded on 09/14/2010 for the course EE 357 at USC.

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Unit12-Interrupts&Timer-EE357-Nazarian-Fall09 -...

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