Unit16-MIPS_ISA-EE357-Nazarian-Fall09

Unit16-MIPS_ISA-EE357-Nazarian-Fall09 - University of...

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Unformatted text preview: University of Southern California University of Southern California Viterbi School of Engineering Viterbi School of Engineering EE357 asic Organization of Computer Systems Basic Organization of Computer Systems IPS ISA MIPS ISA References: 1) Textbook Shahin Nazarian Fall 2009 2) Mark Redekopps slide series Components of an ISA 1. Data and Address Size 8-, 16-, 32-, 64-bit 2. Which instructions does the processor support UBtract struc vs. EGate + ADD strucs SUBtract instruc. vs. NEGate ADD instrucs. 3. Registers accessible to the instructions Faster than accessing data from memory 4. Addressing Modes How instructions can specify location of data operands 5. Length and format of instructions How the operation and operands are represented with 1s and 0s Shahin Nazarian/EE357/Fall 2009 3 MIPS ISA MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages ) is a RISC (Reduced Instruction Set Computing) ISA developed by MIPS Computer Systems (now MIPS Technologies ) The early MIPS architectures were 32-bit, and later versions were 64-bit Computer architecture courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures IPS implementations are currently primarily used in many MIPS implementations are currently primarily used in many embedded systems such as the Series2 TiVo , Windows CE devices, Cisco routers , residential gateways , and video game consoles like the Nintendo 64 and Sony PlayStation , PlayStation 2 , and PlayStation Portable handheld system. Until late 2006, they were also used in many of SGI (Silicon Graphics, Inc.) 's computer products. MIPS implementations were also used by Digital quipment Corporation EC yramid Technology iemens Shahin Nazarian/EE357/Fall 2009 Equipment Corporation , NEC , Pyramid Technology , Siemens Nixdorf , Tandem Computers and others during the late 1980s and 1990s 4 The MIPS ISA we study here! RISC Style 32-bit internal / 32-bit external data size egisters and ALU are 32- its wide Registers and ALU are 32 bits wide Memory bus is logically 32-bits wide (though may be physically wider) egisters Registers 32 General Purpose Registers (GPRs) For integer and address values A few are used for specific tasks/values 32 Floating point registers Fixed size instructions All instructions encoded as a single 32-bit word Three operand instruction format (dest, src1, src2) oad/store architecture ( ll data operands must be in Shahin Nazarian/EE357/Fall 2009 Load/store architecture ( all data operands must be in registers and thus loaded from and stored to memory explicitly ) 5 MIPS Data Sizes Integer 3 Sizes Defined Floating Point 3 Sizes Defined Byte (B) 8-bits Single (S) 32-bits = 4 bytes Half (word) (H) 16-bits = 2 bytes Double (D) 64-bits = 8 bytes Word (W) 32-bits = 4 bytes...
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This note was uploaded on 09/14/2010 for the course EE 357 at USC.

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Unit16-MIPS_ISA-EE357-Nazarian-Fall09 - University of...

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