Unit18-SingleCycleCPU_partI-EE357-Nazarian-Fall09

Unit18-SingleCycleCPU_partI-EE357-Nazarian-Fall09 -...

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University of Southern California Viterbi School of Engineering EE357 asic Organization of Computer Systems Basic Organization of Computer Systems in le ycle PU Single-Cycle CPU Datapath and Control References: 1) Textbook Shahin Nazarian Fall 2009 2) Mark Redekopp’s slide series
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CPU Organization Scope We will build a CPU to implement our subset of the MIPS ISA Memory Reference Instructions: Load Word (LW) tore Word (SW) Store Word (SW) Arithmetic and Logic Instructions: ADD, SUB, AND, OR, SLT Branch and Jump Instructions: Branch if equal (BEQ) Jump unconditional (J) These basic instructions exercise a majority of the ecessary datapath and control logic for a more Shahin Nazarian/EE357/Fall 2009 necessary datapath and control logic for a more complete implementation 2
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CPU Implementations We will go through two implementations Single-cycle CPU ( CPI = 1 ) ll instructi ns execute in a sin le l n cl ck cycle All instructions execute in a single, long clock cycle Multi-cycle CPU ( CPI = n ) nstructions can take a different number of lock Instructions can take a different number of short shortclock cycles to execute Recall that a program execution time is: ( Instruction count ) x ( CPI ) x ( Clock cycle time ) In single-cycle implementation cycle time must be set for longest instruction thus requiring shorter instructions to wait Multi-cycle implementation breaks logic into sub-operations Shahin Nazarian/EE357/Fall 2009 each taking one short clock cycle ;then each instruction takes only the number of clocks (i.e. CPI) it needs 3
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Single-Cycle Datapath To start, let us think about what operations need to be performed for the basic instructions ll instructions go through the following steps: All instructions go through the following steps: Fetch : Use PC address to fetch instruction Decode & Register/Operand Fetch : Determine instruction type and fetch any register operands needed Once decoded, different instructions require different operations ALU instructions : Perform Add, Sub, etc. and write result back to register LW / SW : Calculate address and perform memory access BEQ / J : Update PC (possible based on comparison) et us start with fetching an instruction and work our way Shahin Nazarian/EE357/Fall 2009 Let us start with fetching an instruction and work our way through the necessary components 4
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Fetch Components Required operations Taking address from PC and reading instruction rom memory from memory Incrementing PC to point at next instruction omponents Components PC register nstruction Memory / Cache Instruction Memory / Cache Adder to increment PC value CLK Addr. Data From PC Instruction Word PC + A B S Shahin Nazarian/EE357/Fall 2009 I-Cache / I-MEM Write Register Adder Memory 5
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Fetch Datapath PC value serves as address to instruction memory while whilealso being incremented by 4 using the adder Instruction word is returned by memory after some delay ew PC value is clocked into PC register at end of
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This note was uploaded on 09/14/2010 for the course EE 357 at USC.

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Unit18-SingleCycleCPU_partI-EE357-Nazarian-Fall09 -...

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