EE357-Nazarian-MidtemrII_SampleQuestions-Fall09

EE357-Nazarian-MidtemrII_SampleQuestions-Fall09 - EE 357...

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EE 357 Sample Questions for Midterm II Nazarian Fall 09 1. Short Answer (25 pts.) a. Using the main memory organization discussed in class, when performing consecutive main memory accesses, order the options below from 1 (fastest) to 3 (slowest). ___ Same row, different banks ___ Same row, same bank ___ Different row, same bank b. The interface between the processor core and cache performs transfers of ( single words / blocks ) while the interface between the cache and main memory performs transfers of ( single words / blocks ). c. A 32M x 8 memory chip will require how many address bits? a. 5 b. 8 c. 25 d. 32 d. Caches exploit locality of reference. In an attempt to exploit temporal locality what cache eviction policy would be best? a. Least Frequently Used b. Least Recently Used c. Oldest d. Most Frequently Used e. A 4-way set associative cache with 128 blocks will have how many sets? a. 4 b. 32 c. 128 d. 512 f. A ( fully associative / direct mapped ) cache must search all its entries to determine if the access is a hit and thus ( is physically limited to a small size / can be made fairly large ). g. _______________ puts the burden of checking the status of an I/O device on the processor, while ______________ allows the processor to do other useful work? a. Interrupts / Polling b. Masking / Interrupts c. Busy-looping / Polling d. Polling / Interrupts h. In the embedded system programming labs, if the LSB in an 8-bit register needed to be written with a ‘1’ without affecting the other bits in the register, how could this best be
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EE357-Nazarian-MidtemrII_SampleQuestions-Fall09 - EE 357...

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