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Unit18-SingleCycleCPU-EE357-Nazarian-Fall09

Unit18-SingleCycleCPU-EE357-Nazarian-Fall09 - University of...

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EE357 Basic Organization of Computer Systems Single-Cycle CPU Datapath and Control University of Southern California University of Southern California Viterbi School of Engineering Viterbi School of Engineering Shahin Nazarian Fall 2009 References: 1) Textbook 2) Mark Redekopp’s slide series
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Shahin Nazarian/EE357/Fall 2009 CPU Organization Scope We will build a CPU to implement our subset of the MIPS ISA Memory Reference Instructions: Load Word (LW) Store Word (SW) Arithmetic and Logic Instructions: ADD, SUB, AND, OR, SLT Branch and Jump Instructions: Branch if equal (BEQ) Jump unconditional (J) These basic instructions exercise a majority of the necessary datapath and control logic for a more complete implementation 2
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Shahin Nazarian/EE357/Fall 2009 CPU Implementations We will go through two implementations Single-cycle CPU ( CPI = 1 ) All instructions execute in a single, long clock cycle Multi-cycle CPU ( CPI = n ) Instructions can take a different number of short short clock cycles to execute Recall that a program execution time is: ( Instruction count ) x ( CPI ) x ( Clock cycle time ) In single-cycle implementation cycle time must be set for longest instruction thus requiring shorter instructions to wait Multi-cycle implementation breaks logic into sub-operations each taking one short clock cycle ; then each instruction takes only the number of clocks (i.e. CPI ) it needs 3
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Shahin Nazarian/EE357/Fall 2009 Single-Cycle Datapath To start, let us think about what operations need to be performed for the basic instructions All instructions go through the following steps: Fetch : Use PC address to fetch instruction Decode & Register/Operand Fetch : Determine instruction type and fetch any register operands needed Once decoded, different instructions require different operations ALU instructions : Perform Add, Sub, etc. and write result back to register LW / SW : Calculate address and perform memory access BEQ / J : Update PC (possible based on comparison) Let us start with fetching an instruction and work our way through the necessary components 4
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Shahin Nazarian/EE357/Fall 2009 Fetch Components Required operations Taking address from PC and reading instruction from memory Incrementing PC to point at next instruction Components PC register Instruction Memory / Cache Adder to increment PC value I-Cache / I-MEM Addr. Data From PC Instruction Word PC + A B CLK Write S Register Adder Memory 5
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Shahin Nazarian/EE357/Fall 2009 Fetch Datapath PC value serves as address to instruction memory while while also being incremented by 4 using the adder Instruction word is returned by memory after some delay New PC value is clocked into PC register at end of clock cycle I-Cache / I-MEM Addr.
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