Unit19-MultiCycleCPU-EE357-Nazarian-Fall09

Unit19-MultiCycleCPU-EE357-Nazarian-Fall09 - University...

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University of Southern California Viterbi School of Engineering EE357 asic Organization of Computer Systems Basic Organization of Computer Systems ulti ycle CPU Or anization Multi-Cycle CPU Organization Datapath and Control References: 1) Textbook Shahin Nazarian Fall 2009 2) Mark Redekopp’s slide series
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Single-Cycle CPU Datapath 0 1 + Sh. Left 2 A B 4 PCSrc Control ALUSrc RegDst MemtoReg ranch MemRead & MemWrite 6] ALUOp[1:0] Read Reg. 1 # Read 5 MemRead RegWrite Branch [31:2 6 [25:21] [20:16] I-Cache PC Addr. Instruc. Reg. 2 # Write Reg. # Write Data Read data 1 Read data 2 ALU Res. Zero 0 Addr. ead 0 5 0 1 5 [15:11] Register File Sign Extend 1 D-Cache Read Data Write Data 1 16 32 RegDst ALUSrc MemtoReg LU control INST[5:0] [15:0] Shahin Nazarian/EE357/Fall 2009 2 MemWrite ALU control ALUOp[1:0]
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Multicycle CPU Implementation Single cycle CPU sets the clock period according to the longest instruction execution time Rather than making every instruction “pay” the worst case time, why not make each instruction “pay” just for what it uses Example: Pay Parking Parking meters: Cost proportional to time spent lat fee parking lot: One price no matter the time Flat fee parking lot: Multicycle CPU implementation breaks instructions into smaller, shorter sub-operations Clock period according to the longest sub-operation Instructions like ADD or Jump with few sub- Shahin Nazarian/EE357/Fall 2009 3 operations will take fewer cycles while more involved instructions like LW will take more cycles
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Single vs. Multi-Cycle CPU Single Cycle CPU design makes all instructions wait for the full clock cycle and the cycle time is based on the SLOWEST instruction Multi-cycle CPU will break datapath into sub-operations with the cycle time set by the longest sub-operation. Now instructions only take the number of clock cycles they need to perform their sub-ops struc. Decode / emory rite add Instruc. Fetch Reg. Fetch ALU Memory Access Write Result lw CPI=1 Single-Cycle time Instruc. Fetch Decode / Reg. Fetch ALU Memory Access Write Result lw REG. CPI=n Shahin Nazarian/EE357/Fall 2009 4 time Multi-cycle
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Single-/Multi-Cycle Comparison LK Wasted CLK R-Type CLK R-Type Fetch / Reg. Read / ALU Op / Reg. Write Fetch Reg. Read ALU Op Reg. Write Next Instruc. Wasted Wasted BEQ SW BEQ SW Fetch / Reg. Read / Update PC Fetch / Reg. Read / Calc. Addr / Mem Write. Fetch Reg. Read Update PC Fetch Reg. Read Calc. Addr. Mem Write Next Instruc. Next Instruc. single- cle implementations, the clock multi- cle CPU, each instruction is broken LW Fetch / Reg. Read / Calc. Addr. / Mem Read / Reg. Write Fetch Reg. Read Calc. Addr. Mem Read Reg. Write In single cycle implementations, the clock cycle time must be set for the longest instruction. Thus, shorter instructions waste time if they require a shorter delay In multi cycle CPU, each instruction is broken into separate short (and hopefully time- balanced) sub-operations. Each instruction takes only the clock cycles needed, allowing orter instructions to finish earlier and have Shahin Nazarian/EE357/Fall 2009 5 shorter instructions to finish earlier and have the next instruction start
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This note was uploaded on 09/14/2010 for the course EE 357 at USC.

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Unit19-MultiCycleCPU-EE357-Nazarian-Fall09 - University...

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