chap5(4_in_1)

chap5(4_in_1) - ELEC151 Digital Circuits and Systems...

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ELEC151 Digital Circuits and Systems Lecture Note #5 Sequential Logic • Sequential circuits 5-1 – feedback and clock atches • Latches 5-2 – SR, D and JK latches lip ops • Flip-flops 5-3 – level-sensitive and edge trigger tate transition table and diagram - ) State transition table and diagram (5 4) • State reduction and assignment (5-6) esign procedure of sequential circuit - ) Design procedure of sequential circuit (5 7) • HDL for sequential circuits (5-5) ection 5- ~7 will be covered after Chapter 6 Section 547 will be covered after Chapter 6 eading Assignments: Ho-Chi Huang, Lecture Notes, No. 5-1 Reading Assignments: – Section 5-1, 5-2, 5-3, ELEC151 Digital Circuits and Systems Combinational vs Sequential Logic • Combinational Logic – Outputs are solely determined by inputs epresented by truth table Combinational ircuit Outputs Inputs – Represented by truth table Circuit equential Logic Sequential Logic – There are feedbacks and clocks – Outputs are determined by inputs and feedbacks at clocks Clocks py p – Represented by state-transition diagram or flow chart Next-state Combinational Circuit Output Combinational Circuit Finite States Inputs Outputs Ho-Chi Huang, Lecture Notes, No. 5-2 Feedbacks ELEC151 Digital Circuits and Systems Simple Circuit with Feedback • One inverter with feedback – Self-oscillation, 2 gate delays for one period dd umber of inverters with feedback “0?" "1" – Odd-number of inverters with feedback » self-oscillation of 2x gate delays of one path wo inverters with feedback " " Two inverters with feedback – Memory element (or states) – Basis for commercial static RAM designs "0" 1 – Read-only, but has no write function • Memory with read/write capability – Selectively break the feedback path by transmission gates to load new value into the cell can be written to Z when LD = 1 LD A can be written to Z when LD 1 » Write SW On & Feedback SW Off – Z holds the value when LD = 0 Z LD’ LD’ A Ho-Chi Huang, Lecture Notes, No. 5-3 » Write SW Off & Feedback SW On LD ELEC151 Digital Circuits and Systems Basic SR Latch • Cross-coupled NOR gates – Inverters are replaced by NOR gates R S Q’ Q – 2 inputs, 4 combinations » R=S=0 ==> 2-NOR 1-NOT; Memory =1 S=0 ==> = 0 Q ’= 1; eset » R1 , S0 > Q 0 , Q 1; Reset » R=0, S=1 ==> Q’ = 0 , Q = 1; Set » R=S=1 ==> Q =0, Q’=0 ?; Forbidden ? – Memory, set (write 1) and reset (write 0) functions – What happens if the inputs are changed from R=S=1 to R=S=0 ? » The Q and Q’ cannot be held like a memory, but start racing Ho-Chi Huang, Lecture Notes, No. 5-4
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ELEC151 Digital Circuits and Systems Basic S’R’ Latch • Cross-coupled NAND gates – Inverters are replaced by NAND gates R’ S’ Q Q – 2 inputs, 4 combinations »R ’=S =1 ==> 2-NAND 1-NOT; Memory =1 =0 ==> = 1 Q ’= 0; et » R 1, S 0 > Q 1 , Q 0; Set » R’ =0 , S’ =1 ==> Q’ = 1 , Q = 0; Reset » R’ = S’ =0 ==> Q =1 , Q’=1 ?; Forbidden ?
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chap5(4_in_1) - ELEC151 Digital Circuits and Systems...

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