chap7(4_in_1)

chap7(4_in_1) - ELEC151 Digital Circuits and Systems...

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ELEC151 Digital Circuits and Systems Lecture Note #7 Hardware Description Language • Hardware Description Language 3-9 – Design entry for logic simulation and synthesis wo IEEE standards and many others – Two IEEE standards, and many others »V HDL used in PLD, (originated by DoD, more popular) •VHS IC Very High-Speed Integrated Circuits » Verilog HDL used in textbook, (developed by Cadence) • HDL for Combinational Circuits 4-11 – Boolean expressions – Half adders, decoders, multiplexers, . .. • HDL for Registers and Counters 5-5, 6-6 – Sequential statements atches flip ps registers and counters – Latches, flip-flops, registers and counters, eading Assignments: Ho-Chi Huang, Lecture Notes, No. 7-1 Reading Assignments: – Section 3-9, 4-11, 5-5, 6-6 ELEC151 Digital Circuits and Systems The Elements of Modern Design (from lecture note #1) epresentations Circuit Technologies Rapid Prototyping Design Truth Tables Representations, Circuit Technologies, Rapid Prototyping Representations Boolean Algebra Logic Gates Logic Blocks g Behaviors Waveforms Rapid Prototyping Technologies TTL MOS MOS Simulation Synthesis ROM PAL LA Computer-Aided esign Circuit CMOS BiCMOS PLA SPLD CPLD PGA Design Ho-Chi Huang, Lecture Notes, No. 7-2 Technologies FPGA ELEC151 Digital Circuits and Systems Representation - Behaviors (from lecture note #1) • Behaviors – Textual description of the netlist by hardware description nguage (HDL) BEGIN -- one line for each gate, describing its type and connections i t t PORT MAP ( i 1) language (HDL) i1: inverter_gate PORT MAP (a_in, s1); i2: inverter_gate PORT MAP (b_in, s2); a1: and_gate PORT MAP (b_in, s1, s3); a2: and_gate PORT MAP (a_in, s2, s4); o1: or_gate PORT MAP (s3, s4, sum); END structural; 1 A s3 a1 o1 i1 s1 HDL is perhaps the most important esign representation. There are SUM s4 a2 i2 s2 B desg epese a o eeae two common HDL. One is Verilog HDL used in the textbook, the other VHDL used in the laboratory and Ho-Chi Huang, Lecture Notes, No. 7-3 Carry a3 is VHDL used in the laboratory and lecture notes. We study VHDL . ELEC151 Digital Circuits and Systems VHDL of a Half Adder -- A more completed description NTITY alf adder S ENTITY half_adder IS PORT (A, B: IN STD_LOGIC; Sum, Carry: OUT STD_LOGIC); END half_adder; ARCHITECTURE structural OF half_adder IS COMPONENT inverter_gate PORT (A: IN STD_LOGIC; Z: OUT STD_LOGIC); ND COMPONENT END COMPONENT ; COMPONENT and_gate PORT (A, B: IN STD_LOGIC; Z: OUT STD_LOGIC); END COMPONENT ; COMPONENT or_gate PORT (A, B: IN STD_LOGIC; Z: OUT STD_LOGIC); END COMPONENT ; IGNAL 1 2 3 4 STD LOGIC SIGNAL s1, s2, s3, s4: STD_LOGIC; BEGIN i1: inverter_gate PORT MAP (A, s1); i2: inverter gate PORT MAP (B, s2); _g (, ); a1: and_gate PORT MAP (B, s1, s3); a2: and_gate PORT MAP (A, s2, s4); a3: and_gate PORT MAP (A, B, Carry); 1t ORT MAP 3 4 S ) Ho-Chi Huang, Lecture Notes, No. 7-4 o1: or_gate PORT MAP (s3, s4, Sum); END structural ;
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ELEC151 Digital Circuits and Systems VHDL of a Half Adder -- Inverter gate model nverter gate model -- inverter gate model -- ENTITY inverter_gate IS PORT (A: IN STD_LOGIC; Z: OUT STD_LOGIC); END inverter gate; _g ARCHITECTURE data-flow OF
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This note was uploaded on 09/16/2010 for the course ELEC 151 taught by Professor Cy during the Spring '10 term at HKUST.

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chap7(4_in_1) - ELEC151 Digital Circuits and Systems...

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