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Unformatted text preview: ELEC151 Digital Circuits and Systems HoChi Huang, Lecture Notes, No. 81 Lecture Note #8 Finite State Machine • Analysis of sequential circuit 54 – Mealy and Moore machine – Reverse engineering » From schematics to statetransition diagram • Design of sequential circuit 57 – Design procedure » 7 steps from specifications to schematics • State reduction and assignment 56, 95 – Two most important design steps • HDL for FSM 55 – Sequence detector, and more later • Reading Assignments: – Section 54, 55, 56, 57, 95 ELEC151 Digital Circuits and Systems HoChi Huang, Lecture Notes, No. 82 Finite State Machine and Sequential Logic • Sequential logic and Finitestate machine (FSM) – FSM is a more general term of sequential logic • Storage register – Multiple flipflops (finite states) in parallel – No nextstate and output logic • Shift register – Multiple flipflops (finite states) in series – Might or might not have nextstate and output logic • Conversion of flipflop – One flipflop, one nextstate logic, no output logic Nextstate Combinational Circuit Output Combinational Circuit Finite States Inputs Outputs Feedbacks Clocks ELEC151 Digital Circuits and Systems HoChi Huang, Lecture Notes, No. 83 Finitestate Machine and Counters Nextstate Combinational Circuit Finite States Outputs = states Feedbacks Clocks • Counter has no output logic – The current states are the outputs – Johnson and ring counters have even no nextstate logic • Counter has no data inputs, but only clock input – Proceed through a welldefined sequence of states – No data input to alter the sequence of states • Design of counter – Selection of flipflops – Design of nextstate logic ELEC151 Digital Circuits and Systems HoChi Huang, Lecture Notes, No. 84 Counter Design Procedure • Understand the problem – Statetransition diagram and table – (States are outputs) • Selection of flipflops – T, D and JK flipflops • Design of nextstate logic – Truth table » inputs are current states • (no data inputs) » outputs are inputs to the flipflops • derived by excitation table • (no output logic) • Implementation – Gate counts ELEC151 Digital Circuits and Systems HoChi Huang, Lecture Notes, No. 85 FSM Design Procedure • Understand the problem – Statetransition diagram and table • Number of states could be reduced (State Reduction) – fewer states imply fewer flipflops • Assign binary values to states (State Assignment) – can lead to simpler nextstate and output logic • Selection of flipflops – T, D and JK flipflops • Design of nextstate logic – inputs are current states and data inputs – outputs are inputs to the flipflops • Design of output logic – Truth table is available from the specifications • Implementation ELEC151 Digital Circuits and Systems HoChi Huang, Lecture Notes, No. 86 6 Basic Design Steps of FSM • 1. Understand the Specifications – With a block diagram...
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This note was uploaded on 09/16/2010 for the course ELEC 151 taught by Professor Cy during the Spring '10 term at HKUST.
 Spring '10
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