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Unformatted text preview: Q’ Q D CLK Reset R S Output is cleared to 0 when Reset=1 4. Exercise Design a master/slave D flip-flop with Reset function by Transmission gates --- On Note 5-41 is a master/slave D flip-flop without Reset function by transmission gates Output is cleared to 0 when Reset=1 Note : If we don’t connect the Reset to A (red line), then: when CLK=0 and B = 1 : Reset=1 will make Q=0, but when Reset returns to 0 the Q goes to 1 (because Q follows B) instead of remaining at 0 until next clock cycle. So we need to connect Reset to A as shown above. Reset D CLK’ CLK CLK CLK’ CLK CLK’ CLK’ CLK Q Q’ B A...
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- Spring '10
- Logic gate, 0 k, red line, Reset function, 0 1 2 3 4 5 6 7 J