hw5_sol - Q’ Q D CLK Reset R S Output is cleared to 0...

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ELEC151 – Homework Solution #5 1. The D latch of Fig.5-6 is constructed with four NAND gates and an inverter. Consider the following three other ways for obtaining a D latch. In each case, Draw the logic diagram and verify the circuit operation. a)Use NOR gates for the SR latch part and AND gates for the other two. An inverter may be needed. D CP C Q Q’ S=DC R=D’C b) Use NOR gates for all four gates. Inverters may be needed. D C C Q Q’ S=(D’+C’)’=DC R=(D+C’)’=D’C 2 (a). 3:8 Decoder D >C Q Q’ 0 1 2 3 4 5 6 7 J K C 2 (b). D >C Q Q’ 2:1 Mux 0 1 J K C
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3. Exercise Design an edge-triggered D flip-flop with Reset function by NOR gates --- On Note 5-34 is a D flip-flop with Reset function by NAND gates --- On Note 5-20 is a D flip-flop without Reset function by NOR gates
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Unformatted text preview: Q’ Q D CLK Reset R S Output is cleared to 0 when Reset=1 4. Exercise Design a master/slave D flip-flop with Reset function by Transmission gates --- On Note 5-41 is a master/slave D flip-flop without Reset function by transmission gates Output is cleared to 0 when Reset=1 Note : If we don’t connect the Reset to A (red line), then: when CLK=0 and B = 1 : Reset=1 will make Q=0, but when Reset returns to 0 the Q goes to 1 (because Q follows B) instead of remaining at 0 until next clock cycle. So we need to connect Reset to A as shown above. Reset D CLK’ CLK CLK CLK’ CLK CLK’ CLK’ CLK Q Q’ B A...
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hw5_sol - Q’ Q D CLK Reset R S Output is cleared to 0...

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