hw7_sol _vhdl problems_

hw7_sol _vhdl problems_ - Homework#7 Solution 1 Using...

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Homework #7 Solution 1. Using behavioral architecture design a half adder: ENTITY half_adder IS PORT (A, B: IN STD_LOGIC; Sum, Carry: OUT STD_LOGIC); END half_adder; ARCHITECTURE behavioral OF half_adder IS BEGIN PROCESS BEGIN Sum <= ((NOT A) AND B ) OR ( A AND (NOT B)); END PROCESS; PROCESS BEGIN Carry <= A AND B; END PROCESS; END behavioral; 2. R L
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LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY 4_bit_sr IS PORT ( S: IN STD_LOGIC_VECTOR (1 DOWNTO 0); I: IN STD_LOGIC_VECTOR (3 DOWNTO 0); CLK, CLEAR, LSI, RSI: IN STD_LOGIC; A: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END 4_bit_sr; ARCHITECTURE structural OF 4_bit_sr IS COMPONENT mux4 PORT ( S: IN STD_LOGIC_VECTOR (1 DOWNTO 0); I: IN STD_LOGIC_VECTOR (3 DOWNTO 0); Y: OUT STD_LOGIC); END COMPONENT COMPONENT dffr PORT (D, CLK, RESET: IN STD_LOGIC; Q: OUT STD_LOGIC); END COMPONENT SIGNAL C STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN M3: mux4 PORT MAP (S, I(3), A(2), RSI, A(3), C(3)); M2: mux4 PORT MAP (S, I(2), A(1), A(3), A(2), C(2)); M1: mux4 PORT MAP (S, I(1), A(0), A(2), A(1), C(1)); M0: mux4 PORT MAP (S, I(0), LSI, A(1), A(0), C(0)); D3: dffr PORT MAP (C(3), CLK, CLEAR, A(3));
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