Lab4_1 - Flip-Flops and Sequential Logic I

Lab4_1 - Flip-Flops and Sequential Logic I - Page 1 of 3...

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Unformatted text preview: Page 1 of 3 THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY Department of Electronic and Computer Engineering ELEC 151 Laboratory 4-1 Flip-Flops and Sequential Logic I Grading: s This lab accounts for 2% of your overall grade. A) Objectives: 1. Study the design and implementation of a clock generator using the 555 timer. 2. Familiarize with a commonly available type of flip-flops, namely the J-K flip-flop. 3. Study the design and implementation of flip-flop type conversions. B) Pre-lab Assignments: 1. Read through this lab outline. 2. Answer the questions in the Summary Sheet. 3. Follow the design procedures and design all circuits required. C) Hardware Requirement: Logic Probe, Breadboard; 555 timer IC, Two 0.1 μ F capacitor (mark code= 104) 1 μ F capacitor (mark code=105) Two 470K Ω resistors (Color: Yellow Purple Yellow Gold) Four LED, Four 330 Ω resistors (Color: Orange Orange Brown Gold) 74LS00 (Quad 2-input NAND gate), 74LS14 (Hex Inverter), 74LS74A (Dual D Flip-Flop), 74LS76A (Dual J-K Flip-Flop) ** Please download the datasheet (Or have a copy of the IC pin out before you attend the lab) Page 2 of 3 D) Experiment Procedures: 1. Clock Generator: 555 Timer Output Figure 1: Schematics of the 555 timer chip. A circuit diagram for a clock generator using the 555 timer IC is shown in Figure 1. The period and duty cycle are controlled by placing the appropriate resistors and capacitors...
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This note was uploaded on 09/16/2010 for the course ELEC 151 taught by Professor Cy during the Spring '10 term at HKUST.

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Lab4_1 - Flip-Flops and Sequential Logic I - Page 1 of 3...

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