lab5-3 - THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY...

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Page 1 of 3 THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY Department of Electronic and Computer Engineering ELEC 151 Laboratory 5-3 Counter design using OrCAD PLD Tools with VHDL design entry Grading s This lab accounts for 1% of your overall grade. A) Objectives: 1. To design of a 2-bit decade counter using VHDL design entry. 2. To implement the counter using a GAL22V10. 3. To display binary data in a human readable format. B) Pre-lab -- Design your VHDL code for the implementation of the 2-Digit Decade Counter. C) Hardware Requirement: Breadboard, GAL22V10, 555 timer IC, 0.1 μ F, 1 μ F capacitors, 330 Ω , 470K Ω resistors, LEDs and two 7-Segment Display (common Anode), 74LS47 (BCD to 7-Segment Display Decoder). D) Lab Instructions: 1. Write the VHDL code for the implementation of the 2-Digit Decade Counter. 2. Use the OrCAD PLD software to debug, simulate, compile and build your VHDL for the GAL22V10. You will finally generate 3 files: JEDEC, VHD and LST. The JEDEC file will be used in the second week (Refer to Lab5-1 for the procedure). ** You will get another 0.5% bonus if the hardware part is performed and demo within 1.5 hours . 3. Program the GAL22V10 using the JEDEC file generated by OrCAD PLD from your VHDL file (Refer to Lab5-2 for the procedure). 4. Test your programmed GAL22V10. For this, you must use: (i) The 555 Timer in Lab4-2 to build your clock for the testing of the circuit. (ii) 74LS47 (BCD-to-7-Segment Decoders) to drive 7 Segment Displays (common
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This note was uploaded on 09/16/2010 for the course ELEC 151 taught by Professor Cy during the Spring '10 term at HKUST.

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lab5-3 - THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY...

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