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sol2_07 - 07-1 Flip-flops(20 In the following is a...

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2007 Elec151 Midterm Exam Solution #2, p1/8 07-1. Flip-flops (20%) In the following is a master/slave D flip-flop made of 6 inverters and 4 transmission gates. Replace two inverters by two 2-input NAND gates, so a Negative Asynchronous Reset can be applied to this D flip-flop. The negative Asynchronous Reset can reset Q to 0 immediately and hold the value till the next clocking event. There are many designs. Please provide two different designs. C’ C C’ C Q Q’ C C’ C C’ C C’ D CLK C RESET C D C C Q Q’ CLK C C’ C’ C’ C’ C’ C RESET C D C C Q Q’ C’ C’ C’ C’ C C’ CLK 2007 Elec151 Midterm Exam Solution #2, p2/8 07-2 Asynchronous Counter --- Analysis (15%) For the following asynchronous counter, please draw its state-transition diagram starting from (0 0 0 0). The states are represented by (Q3 Q2 Q1 Q0). (Q3 Q2 Q1) is a modulo 6 counter and (Q0) is a divide-by-2 counter. There will be 12 state transitions Q3 Q2 Q1 Q0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 0 0 (repeat) CLK Clear 0000 0010 0100 1000 1010 1100 1101 1011 1001 0101 0011 0001
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2007 Elec151 Midterm Exam Solution #2, p3/8 07-3 Counter Designs (15%) Use J-K flip-flop as the first flip-flop, D flip-flop as the second flip-flop and T flip-flop as
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