sol2_08 - 08-1 Flip-flops (20%) In the following is a...

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2008 Elec151 Midterm Exam Solution #2, p1/7 08-1 Flip-flops (20%) In the following is a master/slave D flip-flop made of 4 inverters and 4 transmission gates. a) Replace one inverter by a 2-input NOR gate and another inverter by a 2- input NAND gate, and add one more inverter, so a Positive Asynchronous Set can be applied to this D flip-flop. This Positive Asynchronous Set can set Q to 1 immediately and hold the value till the next clocking event. (10%) b) Add a Positive Synchronous Set to this D flip-flop with extra logic gates. The Positive Synchronous Set can set Q to 1 at the clocking event when CLK=1. (5%) c) Write a VHDL code for b) (5%) a) b) c) ENTITY dffs IS PORT (D, CLK, SET: IN STD_LOGIC; Q: OUT STD_LOGIC); END dffs; ARCHITECTURE behavioral OF dffs IS BEGIN PROCESS (D, CLK, SET) BEGIN IF falling_edge(CLK) THEN IF SET=‘1’ THEN Q <= 1; ELSE Q <= D; END IF; END IF; END PROCESS; END behavioral; CLK CLK’ CLK CLK’ D SET CLK’ CLK CLK’ CLK Q Q’ CLK’ CLK CLK’ CLK Q Q’ CLK CLK’ CLK CLK’ D SET CLK’ CLK CLK’ CLK Q Q’ CLK CLK’ CLK CLK’ D
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2008 Elec151 Midterm Exam Solution #2, p2/7 08-2 Reverse Engineering (20%) Find all the state transitions and draw a state transition diagram for the following
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sol2_08 - 08-1 Flip-flops (20%) In the following is a...

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