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Unformatted text preview: 1 Elec Elec Elec Elec 151 Tutorial #7 151 Tutorial #7 151 Tutorial #7 151 Tutorial #7 Outline : • Transmission Gate • Types: SR, JK, D, T Flip-Flops • Latch (level-sensitive) vs Flip-flop (edge triggerred) • Converting from one type of flip-flop to another • Lab 4_1 : Flip-Flops and Sequential Logic I 2 Switches: using n & p transistors control switch open control switch closed Nmos transistor control switch n " 1 " = control n closed switch I " " = control n open switch I=0 1 good 0! bad 1 Pmos transistor control switch p " " = control p closed switch I " 1 " = control p open switch I=0 1 bad 0 good 1! 3 n p Clk Clk …Switches: using n & p transistors I3 I0 I2 I1 A B Z MUX 4:1 (AB = 00 => Z = I0), (AB = 01 => Z = I1), (AB = 10 => Z = I2), (AB = 11 => Z = I3) 1 good 0! good 1! < > I For Clk=1: Switch is off (I=0) For Clk=0 Switch is on (both p and n transistors are on) I Sequential Logic • Combinational logic circuit : the outputs depend solely on the present inputs....
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This note was uploaded on 09/16/2010 for the course ELEC 151 taught by Professor Cy during the Spring '10 term at HKUST.
- Spring '10