tutorial12_4

tutorial12_4 - Project: Lab 6-1 & 6-2 - Finite State...

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Elec Elec 151 Tutorial #12 151 Tutorial #12 Outline : • Project: Lab 6_1 and 6_2: - FSM Design I/II (Sequence detector) Finite State Machine Design: - Moore and Mealy Machine Design - Moore machine vs Mealy Machine - Example of a Moore and Mealy Machine Design - VHDL code for a Moore Machine 2 Design of a Sequence Detector What do we want to design A circuit that investigates an input sequence “x” and will produce an output of “z=1” for any input sequence ending in “1001”. e.g. x = 001001001010 z = 000001001000 We will do: (A) TTL design (no simulations are required, no implementation will be done, just design) (B) 3 … Design of a Sequence Detector (A) Some of the specifications for the TTL design - Require 4 states (Use only 2 FFs: one J-K FF and one D FF) - Assign state '00' to the start state. - Use only the following TTLs: 74LS00 (Quad 2-input NAND) 74LS04 (Hex Inverters) 74LS10 (3-input NAND), 74LS76 (Dual J-K Flip-Flop) 74LS74 (Dual D Flip-Flop) - Design can use up to 9 logic gates (NAND gates and Inverters). - Other specifications/requirements: Read the project specifications posted on the WEB (lab manual) for details. 4 … Design of a Sequence Detector (B) Some of the specifications for the VHDL design & implementation - Require 4 states - Implementation using GAL20V8A. - Negative edge triggered. - Assign state '00' to the start state. -
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tutorial12_4 - Project: Lab 6-1 & 6-2 - Finite State...

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